CIMdata PLM Industry Summary Online Archive

18 January 2005

Product News

Grace and Synopsys Jointly Develop Reference Design Flow

Synopsys, Inc. and Grace Semiconductor Manufacturing Corporation (Grace), a fast growing pure IC foundry located in Shanghai, China, announced that Synopsys' Professional Services group and Grace have jointly developed a reference design flow for Grace's 180 nanometer (nm) processes. The RTL-to-GDSII flow is based on Synopsys' proven GalaxyT Design and DiscoveryT Verification platform. End-users can download the pre-verified reference flow to begin designing and verifying integrated circuits (IC) and be confident that they will achieve predictable, high-quality results. The reference flow is available immediately from Grace.

"We chose Synopsys as our preferred EDA partner to create our first reference design flow because of their reputation in the market and their proven design solution. This relationship gives Grace and its customers a completely integrated, silicon-proven design and verification flow that will speed up product development time for complex 180 nanometer designs," said Dr. Fang Hao, senior director of Technology Development at Grace. "We look forward to working long-term with Synopsys, to help ensure that our customers get the support they need when producing the full range of advanced ICs and systems."

The flow is anchored by Synopsys' Galaxy Design platform, which includes the Design Compiler® synthesis tool, JupiterXTT design planning tool, Physical Compiler® and AstroT physical synthesis solutions, DFT CompilerT test tool, PrimeTime® static timing analysis solution, Star-RCXTT extraction tool, and HerculesT physical verification solution. For design verification, the flow uses the VCS® RTL verification solution and Formality® equivalency checking tool from the DiscoveryT Verification platform were also used. The reference design flow was implemented by Synopsys Professional Services, which has extensive experience creating and deploying design flows for advanced ASICs. The Galaxy Design and Discovery Verification-based flow, optimized for Grace's process technology, will help Grace's customers reduce design times, decrease integration costs and minimize the risks inherent in advanced, complex IC design.

"We're committed to working with Grace to address the needs of the growing Chinese IC market, for advanced process manufacturing capability and proven design methodologies," said Rich Goldman, vice president of Strategic Market Development at Synopsys. "Grace's advanced silicon technologies demand advanced design flows and we're honored that the company chose Synopsys Professional Services and our Galaxy and Discovery platforms to meet those demands. Our collaboration will give Grace and its customers access to a complete portfolio of the leading design and verification solutions."

"The reference design flow for Grace's 180 nanometer (nm) processes will play an active role in the commercialization of scientific research achievements. The EDA Center of Chinese Academy of Sciences will adopt this reference design flow and provide long-term technical support," said Mr. Ye Tianchun, director of the EDA Center of Chinese Academy of Sciences.

As a leading foundry in China, Grace offers customers worldwide a comprehensive set of manufacturing processes through its state-of-the-art fabs. Grace currently supports 250-nm, 220-nm, 180-nm, and 150-nm process technologies, and will soon support 130-nm.

Grace Semiconductor Manufacturing Corporation (Grace) is a pure IC foundry company that specializes in integrated circuit (IC) fabrication. Grace is located in Zhangjiang Hi-Tech Park in Pudong, Shanghai, with a total land area of 240,000 square meters and a first-phase investment of $1.63 billion. Two fabs based on 12-inch wafer specifications have been constructed. Currently, Fab 1A (8") is in full production. It will reach a monthly capacity of 27,000 8-inch wafers by the end 2004. More information about Grace is available at http://www.gsmcthw.com/ .

 

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