CIMdata PLM Industry Summary Online Archive
21 January 2005
Product News
Reshape Releases PD Builder with Support for Cadence Encounter Global Physical Synthesis
ReShape, Inc. announced it has shipped its enhanced PD BuilderT, which supports SoC EncounterT Global Physical Synthesis (GPS) from Cadence Design Systems, Inc. Cadence® SoC Encounter GPS combines RTL synthesis, silicon virtual prototyping, and full chip implementation into a single system. ReShape, working in collaboration with multiple customers that use Cadence software, utilized the PD Builder Open Flow feature to embody expert tool user practices in its programmable reference design flow.
"This release demonstrates how ReShape's Open Flow technology really works to embody the best practices of tool users," said Jim Douglas, president and CEO of ReShape. "Customers leverage PD Builder's architecture, ReShape's reference flow library, and the Open Flow technology to propagate expertise in a scalable and reusable way across the enterprise."
The conventional design flow specification is based on the use of scripting languages such as TCL, Perl, Cadence's SKILL, or Synopsys' Scheme to capture chip construction recipes. These recipes - or scripts - have three problems. First, the scripts are written by engineers for their own use; they are rarely written to be maintained by other engineers, so reuse and maintenance is impractical. As a result, flows are rewritten for every project - squandering precious human resources.
Second, scripts are brittle; they frequently break when chip specifications (netlist, floorplan, IP) change, and designers are forced to recode their scripts. Third, debugging these scripts is painful because they contain hundreds of thousands of lines of script code and are written in a way that binds design specifics such as knowledge of the netlist, floorplan, timing constraints, libraries, and tool versions. It is a huge challenge for the team to locate and fix problems.
PD Builder overcomes these problems by generating a design-specific chip construction recipe at runtime. It "elaborates" the front-end team's netlist and design constraints along with the physical designer's chip construction recipe, using a library of modular flow library elements supplied by ReShape or created using the Open Flow capability. The result is tens of thousands of lines of script customized for the design at hand.
PD Builder's persistent flow execution server then controls the execution of the tens of thousands of commands without human intervention. PD Builder is essentially a flow compiler that in conjunction with commercial physical design tools can build the most complex SoCs in less than 24 hours. PD Builder enables 10X+ runtime reduction on physical design compilation times. Now design teams can explore more design options, quickly verify them to layout quality, and produce SoCs with much greater design margin over conventional methods.
Designers use PD Builder in conjunction with their existing physical design tools from Cadence, Mentor Graphics and Synopsys to perform placement, routing, and sign-off verification functions for their challenging SoC designs.
Availability
PD Builder with support for SoC Encounter GPS from Cadence is available immediately.
Become a member of the CIMdata PLM Community to receive your daily PLM news and much more.
Tell us what you think of the CIMdata Newsletter. Send your feedback.
CIMdata is committed to your privacy. Your personal information will never be sold or shared outside of CIMdata without your express permission.