CIMdata PLM Industry Summary Online Archive
14 February 2005
Company News
Cadence Donates Technology to IEEE to Enhance SystemVerilog Usability
Cadence Design Systems, Inc. announced that it has donated SystemVerilog data type and intellectual property (IP) encryption technology to the IEEE P1800 Working Group to enhance SystemVerilog usability. The IEEE P1800 Working Group will incorporate the Cadence® technology in the first release of the SystemVerilog standard, due later this year. These donations enhance the data types that are currently available in SystemVerilog and enable existing encryption technology to be used to encrypt SystemVerilog code, resulting in enhanced language efficiency and usability.
SystemVerilog enables hardware designers to build on the strengths of Verilog® to help address the challenges in design and verification of next-generation system-on-chip (SoC) devices. The Cadence donation provides enhanced data types that raise the level of abstraction in SystemVerilog, enhancing designer productivity and language usability.
"Cadence has leveraged its leadership in language design and hardware implementation, and is providing valuable technology to designers," said Kevin Silver, vice president marketing for Denali Software, Inc. "Cadence's support for SystemVerilog ensures that the Verilog language will remain a unified industry standard. This unification is very important to users.
"Providing a single language for additional design and verification capabilities reduces the cost of tools and education, and makes it easier for the new technology to be adopted."
The adoption of the Cadence IP encryption technology will allow secure distribution of IP blocks in the standard language. The technology is a major enabler for IP-based SoC design and solves a significant industry problem by providing a standard mechanism for IP protection.
"We've been successfully using this encryption technology with the Incisive functional verification platform using VHDL, and are looking forward to seeing this capability standardized on by all hardware description languages, including SystemVerilog," said Reno Sanchez, director, Microprocessor Center of Excellence, Xilinx. "This encryption technology will make it easier for us to protect our IP as well as help our customers gain access to a broad portfolio of high-value IP, and do so within an industry standards-based protocol."
"In response to our customers' needs, Cadence is driving support for a single Verilog standard that will give users the benefits of open interoperability, exemplified by our recent donations to the IEEE," said Victor Berman, director of Language Standards at Cadence. "Our design and verification platforms, especially the Incisive functional verification platform, are built around open standards that offer customers the flexibility and language choice needed to optimize their verification methodology."
As the initial developer of the Verilog language, Cadence now provides design and verification platform support for SystemVerilog, VHDL, Verilog, PSL/OVL, SystemC, Verilog-AMS and VHDL-AMS. Customers can efficiently run SystemC to verify system function, SystemVerilog and Verilog to verify gate implementation and timing, VHDL for compatibility, PSL for complete assertion-based verification, and AMS for mixed-signal designs. All of these languages now run inside a single simulation interface, allowing customers to use any combination for design and verification to improve language interoperability.
Cadence technologies supporting SystemVerilog include the EncounterT digital IC design platform and IncisiveT functional verification platform, providing customers a powerful option for design, synthesis, formal verification, and acceleration/emulation. For more information, visit http://www.cadence.com/partners/languages/languages.aspx .
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