CIMdata PLM Industry Summary Online Archive
14 February 2005
Company News
Mentor Graphics and Synopsys Offer SystemVerilog Seminars for Users of the Verisity e Language
Two leaders in advanced verification solutions-Mentor Graphics and Synopsys-are presenting a series of free "eScape to SystemVerilog" technical seminars that provide guidance to users of Verisity's e language to transition to a standards-based verification methodology built on SystemVerilog. The first set of seminars in this worldwide series will take place in San Jose on March 2, 2005. Subsequent seminars will take place in Dallas and Boston, with additional locations in North America, Europe, Israel, Japan, Korea, India and Taiwan to be added at a later date.
The "eScape to SystemVerilog" technical seminars will provide practical demonstrations on how users of Verisity's e language can apply SystemVerilog to speed verification and find more bugs, faster. Attendees will learn about SystemVerilog's verification capabilities and gain insight on leveraging these capabilities to increase productivity and design quality. Extensive practical examples will be used to illustrate the verification concepts and methods presented.
Experts in verification methodology and SystemVerilog language features will present the "eScape to SystemVerilog" seminars in an engineering, application-focused fashion. Topics to be covered include language basics, constrained-random test generation, abstraction and reuse, functional coverage, inter-process communication, assertions and verification environment structure.
Seminar Schedule and Locations
The "eScape to SystemVerilog" technical seminar dates and locations in the United States are:
March 2, 2005-San Jose, California
March 3, 2005-Dallas, Texas
March 4, 2005-Boston, Massachusetts
Additional locations will be announced soon. For more details on currently scheduled locations and to register, please visit http://www.systemverilognow.com .
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