CIMdata PLM Industry Summary Online Archive
14 February 2005
Implementation Investments
Aarohi Deploys Synopsys' VCS Native Testbench to Verify Next-Generation Storage Chip
Synopsys, Inc. announced that Aarohi Communications, Inc., a provider of intelligent storage area network components, has adopted Synopsys' VCS comprehensive RTL verification solution, a key component of the DiscoveryT Verification Platform, for the functional verification of Aarohi's next-generation FabricStreamT intelligent storage product. The single-compiler Native Testbench (NTB) technology in the VCS solution will enable Aarohi to increase the performance and effectiveness of their verification environment as compared to using separate testbench and simulation tools. Aarohi selected the latest release of the VCS solution, version 7.2, which extends its NTB capabilities to include functional coverage, Synopsys Reference Verification Methodology (RVM) support and assertion reactivity.
"VCS-our longstanding choice for simulation-now gives us a fully integrated RTL verification solution in a single tool," said Kaushik Patel, vice president of Hardware Engineering at Aarohi. "We have successfully migrated our existing verification environment to the VCS solution with NTB and are using it on our next-generation chip project. Synopsys' VCS NTB capability increases our engineering productivity by providing one integrated solution to power our verification environment, as compared to using multiple tools with our earlier projects."
Latest Version of the VCS Solution Adds New Capabilities
New capabilities in the VCS 7.2 version expand its NTB capabilities and include functional coverage, support for the RVM and assertion reactivity. The functional coverage engine provides a measurement of verification completeness by allowing engineers to specify design functions that should be measured during verification, collect data on exercised functions, and analyze the resulting coverage data. The VCS solution now includes support for the RVM, which embodies years of industry know-how from leading experts on building advanced, reusable verification environments. The RVM includes extensive documentation on testbench architecture and best practices, as well as a library of reusable and extensible testbench and assertion building blocks to reduce verification environment development time and increase bug-finding effectiveness. The VCS solution also provides a comprehensive assertion-checker library and now enables assertion-testbench reactivity for both SystemVerilog and OpenVera® assertions. It supports industry-standard hardware design and verification languages, including Verilog, VHDL, SystemVerilog, SystemCT and OpenVera. The VCS 7.2 version is available immediately.
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