CIMdata PLM Industry Summary Online Archive

14 February 2005

Implementation Investments

NetSilicon Cuts Verification Time and Effort in Half with Synopsys' Vera Tool

Synopsys, Inc. announced that NetSilicon, Inc., a Digi International® Company, achieved first-silicon success using Synopsys' Vera® testbench automation tool and the VCS® comprehensive RTL verification solution as the backbone of its NS9750 NET+ARM processor verification environment. The powerful combination of Synopsys' verification solutions in the DiscoveryT Verification Platform enabled NetSilicon to cut verification time in half and meet an aggressive schedule for delivering samples to initial customers.

"After evaluating available testbench solutions on the market, we selected the Synopsys Vera tool because of its superior capabilities for constrained-random stimulus generation, ease of adoption and evolutionary path to VCS Native Testbench technology," said Brad Hollister, verification lead at NetSilicon. "Even though this chip was more complex than our previous projects, it was functionally correct on first silicon. Doing this project without the Vera tool would have likely required at least twice the number of people and twice the elapsed time."

About the Latest Release of the Vera Tool

The Vera 6.3 version adds numerous productivity enhancements that make it easier to set up a coverage-driven verification environment and debug the results of running constrained-random tests. These enhancements include a new debugger, a VHDL template generator, the Vera tool-to-SystemCT transaction level interface, and several new language features. The tool includes the production release of a completely new high-performance testbench debugger with a faster GUI and added capabilities. It also now has an automated procedure for interface generation, making the connection of VHDL designs to Vera testbenches easier. In addition to pin-level support for SystemC models, version 6.3 adds the capability to pass transaction objects between the Vera tool and SystemC models to facilitate a single testbench for transaction-level and RTL models.

Synopsys Discovery Verification Platform

The Discovery Verification Platform is a unified environment that provides high performance and efficiency of interaction among all platform components, including mixed-HDL simulation, mixed-signal, system-level verification, assertions, verification intellectual property, code coverage, functional coverage, testbenches and formal analysis. Combined with support for industry-standard hardware design and verification languages, including Verilog, VHDL, SystemVerilog, SystemC and OpenVera®, and Synopsys' proven RVM, the Discovery Verification Platform helps designers achieve higher levels of verification productivity by contributing to first-time silicon success within required project cycles.

 

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