CIMdata PLM Industry Summary Online Archive
24 February 2005
Company News
Tensilica Joins EDA Consortium
Tensilica, Inc. announced that it has joined the EDA Consortium. The EDA Consortium represents 100 companies in the $4 billion Electronic Design Automation (EDA) industry and its mission is to promote the health of the EDA industry and to increase awareness of the crucial role EDA plays in today's global economy. Tensilica is a natural addition for the EDA Consortium as its tools, such as the XPRES Compiler, are used to speed the design of complex integrated circuits. Tensilica provides a unique mix of tools and intellectual property (IP) that allow the company to span both of these important industries.
"We are pleased to be joining the EDA Consortium at a time when the electronic design process is starting to go through its next inflection point, up from designing with Verilog or VHDL to designing at higher levels of abstraction to manage both the complexity and time-to-market design issues," stated Chris Rowen, president and CEO of Tensilica. "Tensilica's design tools provide the only automated methodology for complex system-on-chip (SOC) design, both replacing risky hard-wired logic blocks with tiny, fast customized programmable processors, and encouraging rapid platform design based on multiple processors. On average, our customers employ six configurable processors per chip design, achieving an orders-of-magnitude improvement in design abstraction, simulation speed and design productivity."
Key to Tensilica's decision to join the EDA Consortium is the success of its XPRES Compiler, which was introduced last summer. The XPRES (Xtensa PRocessor Extension Synthesis) Compiler enables the rapid development of optimized SOC devices without requiring designers to hand code their hardware using design languages like VHDL and Verilog, a process which can take months or perhaps years of design and verification effort.
With Tensilica's XPRES Compiler, designers simply input the original algorithm that they're trying to optimize, written in standard ANSI C/C++. The XPRES Compiler, coupled with Tensilica's automated processor generation technology, automatically generates an RTL (register transfer level) hardware description and associated software tool chain. In as little as an hour, Tensilica's approach delivers the resulting hardware block in the form of a pre-verified Xtensa LX processor core. The core also enables customers to future proof their designs due to its inherent programmability, and avoid the cost and risk associated with verifying custom logic. Additionally, the generated RTL fully rivals the performance and efficiency of hand-coded RTL blocks with many concurrent operations, efficient data types, and optimized multiple wide deep pipelines.
Become a member of the CIMdata PLM Community to receive your daily PLM news and much more.
Tell us what you think of the CIMdata Newsletter. Send your feedback.
CIMdata is committed to your privacy. Your personal information will never be sold or shared outside of CIMdata without your express permission.