CIMdata PLM Industry Summary Online Archive
28 February 2005
Product News
Novas Extends Industry-Standard Debug Platform for Embedded Processor-Based System-on-Chip Designs
Novas Software, Inc. made a strong push into the electronic system level (ESL) arena today with the introduction of its new nESLT product. The nESL product provides capabilities geared specifically for the 60 percent of today's system-on-chip (SoC) designs that employ embedded processor-based platforms, as well as for designers using advanced system-level design techniques.
The nESL product is an extension of Novas' core debug platform that together with the Company's flagship VerdiT Automated Debug System provides a unified, layered approach to debug that bridges the RTL and system/software domains. New capabilities include: advanced transaction debug and analysis; SystemC compiler, visualization and tracing tools; and hardware-software debug interfaces. These collectively support the higher abstraction and more diverse modeling requirements of embedded system design and verification, as well as the debug of on-chip communications-related structures such as buses, interfaces and IO components.
"As the use of embedded processors becomes commonplace, innovating new ways to understand the behavior of complex design structures and on-chip communications is absolutely fundamental if engineers are to get their jobs done quickly," said Scott Sandler, president and CEO of Novas. "The introduction of our nESL product is a major step forward for SoC debug, and a logical next move for Novas as we continue to expand our solution space to encompass the full range of evolving requirements from systems to silicon."
The emergence of system-level techniques for both embedded processor designs and advanced verification environments introduces new debug requirements beyond traditional hardware description language (HDL)-related methods. Bus-based communication and embedded processors - together with accompanying software, the use of C-based modeling and application-specific pre-designed intellectual property - all add complexity to how a design is debugged by diverse software and hardware teams. These factors are driving the need for an expanded debug platform that enables rapid understanding of the design within its complete verification environment.
The nESL approach tackles this complex process with a single environment that facilitates high-level design methods and provides a common interface for debugging across the entire development flow - from system modeling and simulation-based verification through to emulation of the complete system. It supports multiple languages, transaction-based models and busses, advanced testbench and assertion code, mixed analog/digital signal analysis, hardware/software interaction around industry standard processors and bus structures, as well as the analysis of specific protocols. It also works with specialized tools including software debuggers and rapid prototyping systems.
The first release of the nESL product features a comprehensive transaction viewing environment and powerful suite of analysis tools. The new functionality is built on top of the proven Novas Design Knowledge Architecture, which allows transaction data to come from a number of different sources, including SystemC SCV and "e" sequence descriptions. A variety of transaction styles including split and overlapping transactions can be visualized in a highly intuitive and informative manner. nESL users can also rapidly filter and sort transactions to analyze bus loading or perform source and destination checks.
Also among the notable innovations is the Open Transaction Interface (OTI) that streamlines the capture and storage of transaction data. Designers can easily convert signal information from HDL code, as well as proprietary bus formats, to transactions for abstract viewing. The OTI enables third parties to provide converters and other tools to output transactions. Denali, Inc. (Novas-Denali press release, March 2004) and SpiraTech, Inc. have deployed this use model to output debug information into their transaction-based products.
In addition, Novas is providing a library of bus standards that will operate with a variety of language inputs and cover a range of protocols through an agreement with SpiraTech (see related Novas-SpiraTech release dated February 28, 2005).
"The joint Spiratech/Novas relationship enables transaction level debug for all engineers, eliminating the need for the development of signal-to-transaction abstraction converters by the end-users," said Simon Calder, CEO of SpiraTech. "Leveraging transactions through this unified approach greatly improves an engineer's ability to understand complex design behavior, and will further accelerate debug cycles at the system level now that this technique is accessible with minimal effort."
Pricing & Availability
The new nESL product is purchased as an option to the Novas Verdi Automated Debug System. The U.S. list price starts at $6,000 for a one-year license. The transaction debug and analysis capabilities are immediately available, and the hardware-software debug and SystemC functions are scheduled for limited production availability at the end of the second quarter of 2005.
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