CIMdata PLM Industry Summary Online Archive
12 May 2008
Implementation Investments
Renesas Adopts Cadence SOC Encounter for Large Scale Complex Chips and Flip-Chip Design
Cadence Design Systems, Inc. announced that Renesas Technology Corp. has successfully taped out its most advanced and large-scale system-on-chip (SoC) design to date using the Cadence SoC Encounter™ system. Encounter's complete end to end digital implementation and analysis solution, including innovative design planning, hierarchical modeling, and flip-chip technologies, dramatically reduced design cycle time and silicon costs while accelerating overall timing closure and time to market.
"With SoC Encounter's exceptional memory capacity and fast turnaround time, we were able to tape out our most significant and complex hierarchical design," said Hisaharu Miwa, general manager, Design Technology Division LSI Product Technology Unit at Renesas. "Given the complexity of this design and our aggressive schedule constraints, using a traditional ILM approach to hierarchical design was infeasible, and a new approach was required. SoC Encounter's innovative hierarchical layout handling and 'dynamic' timing modeling technology coupled with its unique automatic floorplan synthesis, and integrated flip-chip features gave us a way to meet our performance and schedule goals while reducing our die-size and manufacturing costs."
"SoC Encounter continues to extend its current lead in providing advanced features and automation to address the needs of very large scale, high-performance, and complex chip design," said David Desharnais, group director of IC Digital product marketing at Cadence. "Renesas' experience and results with SoC Encounter, demonstrates their confidence in its ability to meet and exceed their requirements for advanced designs."
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