CIMdata PLM Industry Summary Online Archive
12 May 2008
Implementation Investments
Socle Technology, Inc. Adopts Cadence Low-Power Solution to Address 65NM Power Efficiency Challenges
Cadence Design Systems, Inc. announced that Socle Technology, a leading system-on-chip design service and solution provider in Taiwan, has adopted the Cadence Low-Power Solution for the Socle SoC-ImP® solution, an ultra-deep submicron implementation platform for SoC design. The Cadence Low-Power Solution enables Socle to leverage innovative low-power techniques to solve power challenges at 65 nanometers and below.
The Cadence Low Power Solution, which is based on the Si2-standard Common Power Format (CPF), has already been used by Socle to tape out an advanced 65-nanometer design with low-power techniques, including multiple power domains, multi-voltage, multi-Vt, power shut-off and retention, resulting in higher productivity while significantly reducing power. The tapeout involved a 65-nanometer ARM926EJ-S®-based media application processor on a Chartered Semiconductor Manufacturing Ltd. process.
"This important tapeout required a comprehensive low-power solution to analyze and manage power throughout the flow, while accelerating the design cycle," said Chou-Te Kang, vice president of R&D of Socle. "The Cadence Low-Power Solution helped our design teams predict and correct problems early in the design process and achieve faster time to market. This successful design experience has led us to join the Power Forward Initiative (PFI), which allows us to work closely together with other industry leaders in delivering high-quality, low-power solutions to our customers."
Socle used the complete Cadence Low-Power Solution, including Incisive® Enterprise Simulator, Incisive Enterprise Manager, Universal Verification Components (UVC), Incisive Plan-to-Closure Methodology (IPCM), Encounter® Conformal Low Power, and SoC Encounter GXL. The integrated, front-to-back low-power verification helped Socle reduce risk and improve design cycle time.
The IPCM, which incorporates the Open Verification Methodology (OVM), helped to more accurately predict the development effort with an automated plan- and metric-driven approach to system-level verification closure. SOC Encounter GXL extended that advantage into physical implementation by providing an integral platform to implement low-power intent while concurrently addressing variation issues at 65 nanometers. Describing designers' power intent with the industry-standard CPF helps eliminate manual effort and the potential for human error in each step of the flow. As a result, Socle was able to harness the efficient and integrated value in the full Cadence Low-Power Solution.
"We are pleased that Socle has adopted the CPF-enabled Cadence Low-Power Solution into their design flow and joined PFI," said Willis Chang, country manager of Cadence Taiwan. "We look forward to working with Socle on additional advanced projects and helping them to realize their aggressive project goals through better schedule predictability and improved team productivity."
About Power Forward Initiative
"The Power Forward Initiative, which has more than 25 member companies, is an industry initiative sponsored by Cadence and has the goal of enabling the design and production of more power-efficient electronic devices. The initiative includes companies representing a broad cross section of the design chain including system, semiconductor, foundry, IP, EDA, ASIC and design services companies. CPF was contributed by Cadence to the Si2 Low-Power Coalition in December 2006 and CPF 1.0 is now available as an Si2 standard to the industry at large. The Initiative has also published A Practical Guide to Low-Power Design — User experience with CPF which is aimed at educating the broad design marketplace in utilizing advanced low-power design techniques. The Guide is available free of charge at http://www.powerforward.org.
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