CIMdata PLM Industry Summary Online Archive
9 June 2008
Product News
Cadence Collaborates With UMC to Deliver 65NM CPF-BASED Low-Power Reference Design Flow
Cadence Design Systems, Inc. and UMC announced the availability of a Common Power Format (CPF)-based low-power reference design flow targeted to the UMC 65-nanometer process. This reference flow enables customers to achieve optimal 65-nanometer low-power designs when used with UMC's Low Power Kit, which includes CPF-enabled libraries and other intellectual property.
This 65-nanometer low-power reference design flow uses UMC's "Leon" test chip as the reference design. Leon is an open source 32-bit RISC microprocessor core with other complex elements including SRAM. The Leon chip was partitioned into multiple voltage domains using the Cadence Low-Power Solution for design, verification, implementation and analysis. As proven with the Leon test chip, the combination of the 65-nanometer reference design flow and the UMC Low Power Kit enables increased productivity while managing design complexity, shortening time-to-market and reducing manufacturing risk.
The UMC 65-nanometer low-power reference design flow highlights key capabilities of the Cadence Low-Power Solution, including Cadence Incisive® Unified Simulator for gate-level low-power simulation; Cadence Encounter® RTL Compiler for synthesis, low-power and DFT cell insertion; Encounter Conformal Low Power for equivalence checking and low power design implementation checking; Encounter Test for ATPG; SoC Encounter RTL-to-GDSII system for floorplanning, powerplan and place-and-route; Encounter Timing System for timing and SI signoff; Cadence QRC Extraction; VoltageStorm® PE for static power and IR analysis; and VoltageStorm DG and Virtuoso® UltraSim for dynamic analysis of current surge at power up. In addition, UMC's Low Power Kit, including its CPF-enabled library, was validated as part of the reference design flow development.
"We are working closely with Cadence to address complex design issues that face designers at 65 nanometers, while enabling faster time to volume through an integrated low-power solution," said Darsun Tsien, UMC's vice president of design methodology. "Through our ongoing collaboration with Cadence, we are able to provide designers with validated low-power technologies to manage power concerns and meet aggressive time-to-market goals."
"This CPF-based flow, the result of a joint effort between Cadence and UMC, accelerates implementation of low-power designs," said Chi-Ping Hsu, corporate vice president of IC Digital and Power Forward at Cadence. "The combination of UMC process technology and the Cadence Low-Power Solution provides our mutual customers with the ability to realize their aggressive project goals while preserving low-power intent throughout the design process."
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