CIMdata PLM Industry Summary Online Archive

9 June 2008

Product News

Synopsys and UMC Release 65-Nanometer Low Power Design Flow Enabled by the Unified Power Format

Synopsys, Inc. and UMC announced the release of a low power design reference flow supporting UMC's 65-nanometer (nm) technology. The new reference design flow includes comprehensive RTL-to-GDSII design capabilities based on the Unified Power Format (UPF) standard and supports methodologies for hierarchical, multi-voltage design, low-leakage libraries from UMC and full integration with Synopsys' Eclypse™ Low Power Solution.

UPF is the industry standard for enabling design teams to specify low power design intent at each stage in the flow. Advanced low power design methodologies demonstrated in the new reference flow include techniques for effectively managing and minimizing dynamic and static power consumption within the design. The Eclypse Low Power Solution, which supports advanced techniques including power shut-down, clock gating, Multi-Vt, dynamic voltage and frequency scaling (DVFS), helps manage these design challenges via its UPF support, which spans the entire design flow. Combined with unique capabilities including voltage-aware verification with automated multi-voltage assertions, automated power gating and enhanced low power clock-tree synthesis, this solution adds new capabilities to enhance the UMC 65-nm low power design flow.

The new low power design reference flow utilizes UMC's 65-nm low-leakage libraries to take advantage of multi-voltage and power gating techniques by integrating UMC's low-power intellectual property (IP). Synopsys Professional Services and UMC validated the new low-power design reference flow using the "LEON" open-source 32-bit RISC microprocessor core, which is partitioned into multiple voltage regions. The validated reference design is highly configurable and expandable with additional digital and analog/mixed-signal IP modules.

"We have partnered with Synopsys to bring proven low power capabilities to our customers," said Stephen Fu, director of Digital IP Development Division at UMC. "The flow, enabled by UPF, represents the latest techniques to address the power design needs of our mutual customers and shortens the time to market with a validated flow for UMC's advanced processes."

"Synopsys' low power technology is an integral part of the 65-nanometer low power design reference flow developed in partnership with UMC," said Rich Goldman, vice president of Corporate Marketing and Strategic Market Development at Synopsys. "Our collaboration resulted in a low power design reference flow offering silicon-proven methodologies and techniques from Synopsys coupled with trusted IP and manufacturing expertise from UMC -- providing our customers with the latest technology and innovative design solutions."

Availability

The UMC/Synopsys 65-nm low power design reference design flow enabled by UPF is slated for availability in August 2008, via http://www.umc.com/. Customers should contact UMC for more information.

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