CIMdata PLM Industry Summary Online Archive
10 June 2008
Product News
Magma and UMC Announce UPF-Compliant Low-Power Reference Flow
Magma® Design Automation Inc. and UMC announced the availability of a validated UPF-compliant low-power RTL-to-GDSII design flow that uses the UMC 65-nanometer (nm) library. Based on the Talus® IC implementation system, including Talus Power Pro, and the unified Magma design environment, the flow uses advanced low-power design methodologies to minimize power consumption while maximizing quality of results and reducing design iterations.
The validation process included implementing a complex low-power design using a Unified Power Format (UPF)-compliant specification to drive automatic creation of multiple power domains, including level-shifter, isolation-cell and retention-flop insertion. The design flow demonstrated UPF-compliant results and power reduction using the UMC 65-nm process and low-power library
"The Magma-UMC UPF-compliant Low-Power Reference Flow offers significant advantages," said Ming Hsu, vice president of Worldwide IP Support at UMC. "The Magma software supports UPF while enabling advanced techniques, including automated multi-voltage designs, ultra low-power clock tree synthesis, and physical implementation, that meet dynamic and leakage power requirements. UMC's process technology offers low-leakage transistors to help further reduce IC power consumption."
"Many of Magma's customers develop ICs for wireless and portable consumer devices, which require fast turnaround time and low power consumption," said Kam Kittrell, general manager of Magma's Design Implementation Business Unit. "The UPF allows designers to specify power intent once and use it throughout the design flow, saving time and reducing power. By collaborating to deliver a UPF-compliant flow, Magma and UMC provide designers with a streamlined flow from RTL to low-power silicon."
Talus: An Advanced Low-Power Design Flow
The Magma-UMC UPF Low-power Reference Flow is based on the Talus implementation system. This system provides a fully integrated RTL-to-GDSII flow for high-performance, high-complexity, low-power nanometer designs. Talus Design and Talus Vortex are key components of the system. Talus Design is a full-chip synthesis environment that enables rapid development of RTL and chip-level constraints throughout the design process, and automates data-path synthesis and floorplan generation for prototyping. Talus Vortex is a physical design environment that delivers improved timing and signal integrity, smaller area, lower power, better manufacturability, faster turnaround time and higher capacity than conventional point-tool flows.
Talus Power Pro works in conjunction with Talus Design and Talus Vortex to enable optimal power management throughout the flow. It features power-aware synthesis, physical optimization, clock tree synthesis and routing, allowing designers to minimize power and ensure uniform power distribution.
Talus Power Pro reads in the power constraints from the UPF file at the beginning of the RTL-to-GDSII flow. Power constraints such as clock gating, retention-flop synthesis and multi-Vdd domain definitions can be defined for dynamic power reduction. Special cells such as level shifters and isolation cells can be inferred during the synthesis stage to support multi-Vdd flows. For domains that are powered down, switches can be inferred at the RTL stage to facilitate simulation. State tables can be used to define the relationship between the different domains that have been created. Talus Power Pro can also write out UPF files at any point in the design flow for easy interoperability with third-party tools.
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