CIMdata PLM Industry Summary Online Archive
9 June 2008
Product News
Mentor Graphics Outlines IC Implementation Strategy to Address Sub-45nm Challenges
Mentor Graphics Corporation laid out its integrated circuit (IC) implementation strategy to help customers with the challenges they face as they move to smaller process nodes. A first step in this strategy was the merging of several offerings into a single Design-to-Silicon division: the Calibre® physical verification and Design-for-Manufacturing (DFM) platform, the Olympus-SoC™ place-and-route system (from last year’s Sierra Design Automation acquisition), and the Mentor Design-for-Test and Yield Learning solution. The recently acquired assets of the Ponte Solutions organization and NXP Semiconductors Germany DFT technology further augment the resources of the division. With this new alignment Mentor has begun to drive the integration of its three industry-leading platforms based on a common vision for delivering first-pass silicon success.
“We are aligned with customers in our vision of how to meet future challenges, and have a strong technology roadmap to deliver new capabilities through platform advancements and cross-platform integration,” said Joseph Sawicki, vice president and general manager, Design to Silicon Division, Mentor Graphics. “We’re engaged with our customers on a day-to-day basis in their design labs and fabs to ensure the Mentor offerings truly resolve customer needs at each step.”
“We have collaborated with Mentor Graphics for many years to address IC implementation challenges at each successive technology node,” said Philippe Magarshack, STMicroelectronics Technology R&D Group Vice President and Central CAD and Design Solutions General Manager. “We were also working with Sierra Design Automation before the acquisition by Mentor, and we encouraged the integration of Olympus-SOC and Calibre technologies to address the increasing challenges we foresee at 32/22nm. We believe the Mentor solution will help us meet critical IC implementation challenges such as the complexity of multi-mode, low power designs, designing for high manufacturing yields, and achieving market-leading performance.”
New platform capabilities discussed at the Design Automation Conference being held this week include:
• The Equation-based DRC facility of the Calibre nmDRC platform, which allows users to easily implement advanced multi-dimensional (2D/3D) physical verification (PV) checks that are difficult, if not outright impossible, to perform today with other offerings.
• A new distributed computing implementation of the nmDRC platform that significantly reduces memory requirements while at the same time improving runtime.
• Incremental verification features that allow multiple design rule checking runs to execute in parallel.
• A CMPAnalyzer planarity solution that optimizes metal fill for best performance using both CMP models and layout density analysis.
• A new Calibre nmLVS tool with interactive debugging features (to be released to the general market in the second half of 2008) that will speed layout-versus-schematic checking with automated suggestions for fixing the design, improved short identification, and overall improvements to the environment to reduce debugging time.
Mentor also outlined plans for integration across their three major IC implementation platforms. The success of the Olympus-SoC/Calibre LFD™ (Litho-Friendly Design) solution for avoidance of litho hotspots during routing will be extended with further integration of Calibre models early in the floorplanning and routing process. Concurrent Multi-Corner Multi-Mode optimization with silicon-proven Calibre DFM models will enable the Olympus-SoC product to create DFM-optimized designs in a single pass, significantly reducing the time required to reach tapeout, while at the same time allowing designers to immediately see the impact on manufacturability, timing, power, signal integrity and other chip performance factors.
DFT integration with physical analysis currently provides targeted test generation for specific DFM hotspots using the TestKompress® ATPG solution. Likewise, integration between physical analysis and the YieldAssist™ product allows direct viewing of suspect defect locations for reduced failure analysis turnaround time. Going forward, further integration will help customers to rapidly find the root causes of manufacturing defects by being able to quickly identify hidden systematic yield limiters by analyzing volume production test data with new software techniques. Designers can also use the results of yield learning to re-prioritize and tune their recommended design rules throughout the lifecycle of a product offering.
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