CIMdata PLM Industry Summary Online Archive

18 June 2008 1 2008

Product News

Synopsys' DesignWare Verification IP Enhanced to Support New SATA 6Gbps Specification

Synopsys, Inc. announced that its DesignWare® SATA Verification IP now supports SATA 6Gbps transfer rates as defined in the draft Serial ATA International Organization: Serial ATA Revision 3.0 specification. The third generation of the SATA specification doubles the data transfer rate of the 2.6 specification from 3Gbps to 6Gbps, enabling designers to take advantage of the increased throughput rates to move large amounts of data, such as high resolution photos, videos and music. Designers who want to implement a SATA 6Gbps interface can now use DesignWare Verification IP to significantly speed testbench development time and quickly verify their mass storage system-on-chip (SoC) designs.

The DesignWare Verification IP supports all major simulators and verification languages including Verilog, SystemVerilog, VHDL and Vera, allowing designers to create a comprehensive SATA- based environment. In addition, the Verification IP for SATA delivers up to 5X performance improvement when used with Synopsys' VCS® simulation tool. Synopsys' comprehensive solution also includes the DesignWare digital controllers and PHY IP for SATA, providing designers with access to a complete SATA solution from a single IP vendor.

"Verification IP plays a critical role in lowering the testbench development time and cost by reducing the need to create a verification environment from the ground up," said John Koeter, senior director of marketing for IP and Systems at Synopsys. "The DesignWare Verification IP with support for 6Gbps enables designers to quickly take advantage of the latest specifications, while lowering integration risk and speeding their product development time."


The DesignWare Verification IP for SATA with support for 6Gbps is available today as a standalone product, both in the DesignWare Library and VCS Verification Library. For more information, please visit

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