CIMdata PLM Industry Summary Online Archive
8 September 2008
Product News
Cadence Extends Low-Power Leadership With Early Dynamic Power Analysis and Pre-RTL Exploration
Cadence having established the Cadence® Low-Power Solution as a leader in design, implementation and verification systems for advanced low-power chips, Cadence now addresses designers’ next critical need – faster power exploration and estimation - earlier in the product design lifecycle.
Cadence Incisive® Palladium® Dynamic Power Analysis enables SoC designers, architects and validation engineers to estimate the power consumption of their system during the design phase, analyzing the effects of running various real software stacks and other real-world stimuli. The new offerings also include the Cadence InCyte Chip Estimator, which can now provide what-if power analysis through exploration of different low-power techniques. The InCyte Chip Estimator also generates automatically the Si2 Common Power Format (CPF), which helps drive architectural power specification and intent into implementation and verification.
The Palladium Dynamic Power Analysis innovation presents a methodology shift for power budgeting of electronic devices with system-level implications. With a focus on productivity improvement, Palladium Dynamic Power Analysis helps to identify the average and peak power consumption of SoC designs running real software in various operational scenarios. Leveraging Palladium III built-in memory and RTL Compiler power estimation engine, Cadence provides a first high-performance, cycle-accurate integrated solution delivering full-system power analysis of designs, including both hardware and software.
"As an industry, we’ve only begun to realize the benefits of power efficient design," said Will Strauss, principal wireless analyst for Forward Concepts. "At the same time, consumers are demanding more applications and greater performance with the same or better battery life and footprint. What Cadence delivers is a unique ability to analyze and verify power tradeoffs at the point where hardware and software design converge – the system level, where chip design can impact system software performance and vice versa. There’s a great need for faster, easier and more efficient power design at this level."
Delivering on customer requirements for even earlier power exploration and estimation, the Cadence InCyte Chip Estimator now offers low-power planning capabilities, including automatic creation of the Common Power Format. This allows designers to perform accurate pre-RTL estimation of die size, performance and cost, enabling early exploration of the design impact of various low-power techniques. The InCyte Chip Estimator can be used to author and explore CPF scenarios and interfaces into downstream Cadence implementation, RTL simulation and emulation tools that drive low-power strategy through the design methodology.
"Pre-silicon system-level power analysis and exploration require a broad view of power requirements and a detailed view of power consumption with real scenarios," said Ran Avinun, product marketing group director for system design and verification at Cadence Design Systems. "Palladium Dynamic Power Analysis and InCyte Chip Estimator provide automated processes and capabilities early in the design process, taking in consideration the technology libraries, the embedded software and the real stimuli to ensure system power budget constraints are being met with the real environment at first silicon with first working software phase."
InCyte Chip Estimator and Palladium Dynamic Power Analysis are available immediately and will be demonstrated at CDNLive! Silicon Valley to be held at the San Jose Convention Center, September 9-11 2008. The Palladium Dynamic Power Analysis product is being sold as an option for the Palladium III system.
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