CIMdata PLM Industry Summary Online Archive
13 October 2008
Product News
Mentor Graphics Olympus-SoC Place-and-Route System Slashes Design Closure Times with Industry’s First Parallel Timing Analysis and Optimization Technology
Mentor Graphics Corporation announced the immediate availability of new task-oriented parallelism technology in the Mentor Graphics Olympus-SoC™ place-and-route system that allows timing analysis and optimization tasks to run in parallel to deliver up to 7X improvement in timing analysis run times, and up to 4X improvement in design closure times using eight CPU cores.
“We used the new timing and optimization technology in Olympus-SoC for the extremely complicated EMMA design, which has over 30 million gates, four modes and four corners, a 200MHz main clock, and over 150 derived clocks,” said Mr. Masao Hirasawa, General Manager, Digital Consumer LSI Division, NEC Electronics Corporation. “The proven EMMA platform is specifically designed to deliver versatility and performance for digital AV applications, such as STB (Set-Top-Boxes), digital TVs, and DVD recorders through MPEG signal processing core technology. Achieving design closure within our aggressive schedule was a huge challenge for us. We are very impressed with Olympus-SoC’s performance improvements, which provided almost a factor of four reduction in our design closure time. We continue to be very happy with the overall performance and productivity improvements we’re getting with Olympus-SoC in our design flow.”
“Rapid physical design closure for advanced 65, 45 and 40 nanometer SoC designs is critically important to our competitiveness, and we’re always looking for the best technology to meet aggressive time-to-market pressure,” said Shoji Ichino, general manager of the Technology Development Division at Fujitsu Microelectronics Limited. “The Olympus-SoC place-and-route system is already part of our Reference Design Flow (RDF) kit, which is being used for many advanced designs to rapidly close complex multi-corner multi-mode (MCMM) design issues. Now the new fully-parallelized Olympus-SoC timer will give us much faster turnaround for those design closures by taking full advantage of the most advanced multicore processors.”
Reducing Design Closure Times with Multicore Processing
The latest integrated circuits (ICs) require exponentially increasing processing power to reach physical design closure within tight time-to-market schedules. Design sizes continue to increase with Moore’s Law, complicated by manufacturing variability and signal integrity issues that require closure over many design and process modes and corners. The best way to gain additional speed is to apply the full power of multicore processors to the most compute-intensive aspect of the flow—timing analysis and optimization related tasks. However, traditional place-and-route architectures are not able to take full advantage of multiple processors within the timing kernel, severely limiting their scalability on multicore platforms.
The Olympus-SoC place-and-route system addresses this challenge with a combination of key technologies collectively referred to as task-oriented parallelism. Mentor’s task-oriented parallelism technology is a fine-grained, lockless technique that for the first time allows parallelization of the most compute intensive analysis and optimization tasks within the place-and-route timing kernel. A compact data structure with an unlimited number of virtual timing graphs makes the Olympus-SoC system inherently efficient for complex MCMM analysis. To fully utilize advanced multicore processors, the Olympus-SoC system employs sophisticated dataflow analysis that allows parasitic extraction, delay, MCMM signal integrity (SI), timing, and power analysis tasks to be done in parallel on many CPUs without the locking and synchronization overhead inherent in traditional architectures. In addition, it automatically determines the optimum strategy for partitioning, and fine-grained and coarse-grained parallelization, for each specific IC design flow step to ensure the best quality of results (QoR) and turnaround time (TAT) for a specific layout. As a result, the Olympus-SoC system scales linearly as CPUs are added, enabling customers to complete even their largest designs on schedule.
“Leading-edge customers are increasingly turning to the Olympus-SoC solution to get the best quality of results and the shortest design times,” said Joseph Sawicki, vice president and general manager for the design-to-silicon division at Mentor Graphics. “Other place-and-route tools boast multithreading and multitasking capability, but no other product has a parallel timing analysis engine at its core to deliver fast multi-corner multi-mode analysis and optimization, and this is ultimately what determines overall time to design closure. Successes on high-end SoC products demonstrate the Mentor difference and why customers are standardizing on our solution for their high-end products.”
Pricing and Availability
Task-oriented parallelism, an add-on option to the Olympus-SoC place-and-route system, is available now and is priced starting at $180K.
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