CIMdata PLM Industry Summary Online Archive
15 October 2008
Acquisitions
Cadence Expands Enterprise Verification IP Portfolio by 5X to Provide Industry's Broadest OVM Multi-language Offering
Cadence Design Systems, Inc. announced that it has acquired the verification IP (VIP) assets from leading providers Yogitech SpA, IntelliProp Inc., and HDL Design House. With the addition of these high-quality components, Cadence® expands its existing VIP portfolio by five times to now include over 30 standard protocols for wireless, networking, storage, multimedia, automotive, and more, also enabling Cadence to better address and help customers resolve their key business risk areas of schedule and design process predictability, design team productivity, and end product quality. Purchase terms were not disclosed.
This asset acquisition allows Cadence to leverage its existing leadership in VIP capability, including Open Verification Methodology (OVM) multi-language reuse, protocol compliance, and automated metric-driven verification methodology. Unlike alternative VIP offerings in the market today that provide basic bus-functional model (BFM) capability, all of the Cadence Incisive® Universal Verification Components (UVC) in the portfolio will provide a pre-packaged metric-driven solution. This includes OVM multi-language support for both SystemVerilog and e, and the industry-unique Compliance Management System to measure compliance against the protocol specification. In addition, the UVCs include all of the advanced testbench features Cadence customers have come to expect, such as constrained-random stimuli generation, complete protocol checking, scoreboarding hooks, and a full functional coverage.
"Cadence is taking a prime position in the breadth of verification IP offered with this announcement," said Ian Mackintosh, president and chairman of OCP-IP. "OCP implementers will certainly benefit from the availability of both advanced testbench and assertion based VIP for OCP from a single vendor – especially with the compliance checks built right in."
"Cadence has long provided industry leadership in verification technology and methodology as this has been both a critical and growing problem our customers face while designing their complex SoCs," said Tom Cooley, corporate vice president of marketing and field operations at Cadence. "The acquisition of powerful, mature verification IP from leading verification providers Yogitech, Intelliprop, and HDL Design House allows Cadence to provide the broadest offering of proven verification IP and accelerate our customers’ ability to quickly achieve verification closure and meet their business objectives."
Customers developing today’s IP and SoC designs face the challenge of high complexity and shrinking schedules, and requires the scalable, consistent adoptability and reusability attributes provided by an OVM multi-language environment. OVM has enjoyed tremendous customer adoption and growth in vendor support since its open-source release on www.ovmworld.org. As a co-developer of OVM and contributor to the open source community, Cadence has invested in providing the broadest portfolio of multi-language OVM VIP, providing leadership to the industry and accelerating the momentum of the ecosystem.
The OVM and Cadence Incisive verification technology support within the VIP allows teams to create, integrate, and reuse their verification environments from block to chip to system level than other less capable offerings in the market. This significantly reduces their verification risk by dramatically shrinking verification environment development and bring-up time, ensuring compliance to the protocol specifications being implemented or integrated, and automating the collection and analysis of verification metrics to rapidly achieve verification closure.
"Yogitech has a successful history of providing specialized solutions consisting of products, methodologies, and services for digital and mixed-signal design and verification to key leaders across the semiconductor industry, and we’re now strengthening our unique solution offering in the domain of safety-critical electronics," said Silvano Motto, president and CEO of Yogitech. "As an early verification collaborator with Cadence, we have worked closely on verification technology and reuse methodology and see our contribution to Cadence’s VIP portfolio and this next phase of our relationship providing tremendous value to the end customer in terms of broad availability and applicability of this industry-leading VIP offering."
Expanded Protocol Support
The existing portfolio of Cadence UVCs supports AMBA AHB and AXI, Ethernet, PCI Express, PCI, and USB industry-standard protocols. The new offering will better address VIP needs across major market segments, with the expanded portfolio including support for the following additional protocols:
AMBA APB |
ATAPI |
CAN |
CE-ATA |
CompactFlash |
DDR2 |
DDR3 |
FibreChannel |
HDMI |
HyperTransport |
I2C |
JTAG |
LPC |
LIN |
OCP |
PCI-X |
PMBus |
Register & Memory |
SAS |
SATA |
SDIO |
Serial Rapid I/O |
SMBus |
SPI-4 |
Cadence customers already benefit from the company's long history of expertise and industry success in the creation and deployment of advanced testbench, assertion-based and transaction-based acceleration VIP in addition to its SpeedBridge® adapters for emulation and in-circuit system validation. The availability of this broad range of VIP addresses project requirements for standard protocol IP acceptance, compliance, and SoC integration -- from the enterprise-wide needs at large corporations to individual projects at small start-ups.
Additional Quotes:
"Intelliprop has leveraged its position of providing leading design and verification services, IP, and VIP for the storage market segment for over 10 years to help customers achieve the design quality and process effectiveness needed to make their products successful," said Hiren Patel, president and CEO of Intelliprop. "Cadence has consistently driven the state-of-the-art in verification technology, methodology, and reuse, and has clearly positioned itself to not only provide the leading VIP offering for the storage market segment, but easily the most robust offering for anyone doing SoC or IP design."
"As an ASIC and SoC design and verification services and IP company, HDL Design House has a long track record of working with customers to successfully face difficult schedule, complexity, and cost challenges through our expertise in verification methodology and reuse," said Predrag Markovic, president and CEO of HDL Design House. "We see this transaction as the next step in our long relationship with Cadence to provide their customers with the best-in-class advanced verification IP for their broader SoC verification challenges."
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