CIMdata PLM Industry Summary Online Archive
29 October 2008
Implementation Investments
Moai Electronics Accelerates Flash Memory Controller Tapeout with Cadence Logic Synthesis and DFT Solutions
Cadence Design Systems, Inc. announced Moai Electronics Co., a leading IC design company in Taiwan, has deployed Cadence® Encounter® RTL Compiler and Encounter Test to successfully tape out a flash memory controller with dramatically faster time to market, lower test costs, and higher quality.
The joint use of Encounter RTL Compiler global synthesis and Encounter Test enabled Moai’s design team to improve the RTL to ATPG turnaround time from weeks to days. The single flow for logic and DFT synthesis provided greater design optimization, ease of use, and increased productivity. The advanced fault modeling capability and flexible compression strategy provided higher quality while meeting aggressive tester pin-count cost goals.
“With Encounter RTL Compiler and Encounter Test, we are able to reduce test data volume and test application time, and achieve better timing convergence during physical implementation,” said P. F. Lin, President of Moai Electronics Co. “This outstanding result enabled increased quality for the end product, which is solid proof of the value of Cadence’s highly integrated design and test environment.”
“Moai has seen first-hand how Cadence Encounter RTL Compiler and Encounter Test technologies can enhance flash memory controller design,” said Lung Chu, president of Asia Pacific for Cadence Design Systems. “We are happy to assist Moai in developing next-generation chip designs and look forward to enabling greater successes with the Cadence digital design solutions.”
Encounter RTL Compiler and Encounter Test are key components of the Cadence Logic Design Team Solution and digital implementation user segments. In addition to a complete one-pass global logic-test synthesis flow, the environment provides access to all DFT functionality, including Memory BIST, test point insertion, multiple compression architectures, and sophisticated masking for compression. Other core strengths of this integrated flow are an ultra-fast DFT rule checker with RTL feedback, power-aware scan synthesis and ATPG solution, and physically-aware scan synthesis.
Become a member of the CIMdata PLM Community to receive your daily PLM news and much more.
Tell us what you think of the CIMdata Newsletter. Send your feedback.
CIMdata is committed to your privacy. Your personal information will never be sold or shared outside of CIMdata without your express permission.