CIMdata PLM Industry Summary Online Archive
13 November 2008
Implementation Investments
NEC Electronics Selects Mentor Graphics Calibre nmLVS for Advanced Circuit Characterization at 40nm and Below
Mentor Graphics Corporation announced that NEC Electronics Corporation (Kanagawa, Japan) has selected the Calibre® nmLVS product to establish a highly accurate circuit characterization flow for 40nm and below. The Calibre nmLVS verification tool has been enhanced and upgraded for nanometer large-scale integrated circuits (LSI) with new features including advanced device parameter (ADP) extraction to enable customer-specific circuit characterization, as well as greater interactive debugging capabilities, and improved performance to increase productivity and reduce cycle times for very large SoC devices.
“Mentor’s Calibre nmLVS product with the ADP extraction feature enables us to extract highly-accurate circuit characteristics better reflecting our industry-leading semiconductor processes by taking into account systematic variation of layout context among the transistors themselves, and within the surrounding region,” said Haruji Futami, Senior Manager, Core Development Division, Technology Foundation Development Operations Unit. “This capability allows NEC Electronics to ensure more accurately designed LSI without any additional changes to our existing design flow. For this reason we are incorporating Calibre nmLVS into our standard design flow for high-density, high-performance LSI development, starting with products implemented at 40nm and below.”
NEC Electronics uses the Calibre nmLVS solution in a design flow that estimates the systematic variation in electric characteristics caused by differences in the way layout shapes are implemented on the wafer, which is a growing concern at smaller process geometries. The Calibre nmLVS tool accurately extracts circuit values taking into consideration interactions among adjacent gates, and stress effects introduced by shallow trench isolation (STI). By using a new script developed by NEC Electronics, extracted geometric data is fed into NEC Electronics’ proprietary gate pitch dependent characteristics variation model, and an STI stress induced characteristics variation model, which was developed by the MIRAI project lead by Selete under contract to NEDO (New Energy and Industrial Technology Development Organization). The Calibre nmLVS tool uses both models described in the script to generate a systematic variation aware net list. “We will continue to incorporate results from the MIRAI project and other layout-based variability factors into our design flow to further improve the accuracy of our LSI development," added Mr. Futami.
“Meeting the needs of our customers working at leading edge process nodes requires us to evolve our tools at every step of the IC implementation flow,” said Joseph Sawicki, vice president and general manager for the design-to-silicon division at Mentor Graphics. “Because our solutions are all based on a common Calibre nm Platform, we can provide functional and performance advancements in a timely and consistent manner, enabling our customers to create highly flexible and well-integrated flows.”
Pricing and Availability
The Calibre nmLVS solution is available now. Pricing starts at $126K.
About NEDO, Selete, and MIRAI
NEDO (New Energy and Industrial Technology Development Organization) is one of the largest central R&D organizations in Japan created to promote research, development and proliferation of Japanese industrial technologies and energy/environmental technologies. Selete (Semiconductor Leading Edge Technologies) was established with investment from eleven Japanese semiconductor firms including NEC Electronics as a consortium. MIRAI is a government research project under a research contract with NEDO, to develop technology innovation to tackle the challenges in the technical areas of hp45nm and below. Selete is a key member in this project.
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