CIMdata PLM Industry Summary Online Archive
30 January 2008
Product News
Magma Announces Validated RTL-to-GDSII Low-Power Reference Flow for UMC’s Advanced 65-Nanometer Process
Magma® Design Automation Inc. announced the availability of an integrated low-power IC implementation reference flow for UMC’s advanced 65-nanometer (nm) process. The 65-nm low-power reference flow enables designers to address low-power nanometer design considerations during implementation and within a single environment, maximizing quality of results (QoR) while reducing turnaround time. A similar low-power reference flow for 90-nanometer has been available since 2006.
UMC’s validation of the Magma low-power flow, which included rigorous QoR testing on actual designs, ensures that mutual customers have a streamlined path from RTL to silicon for their 65-nm chips.
“Addressing low-power considerations within our reference flows is critical to design success at advanced process nodes,” said Ming Hsu, vice president of Worldwide IP Support at UMC. “We worked closely with Magma during the development of this 65-nm low-power reference flow to ensure that our process technology and the Magma software address many of the low-power requirements that designers are facing at 65 nm.”
"With this reference flow, we continue to grow as an integral part of UMC’s foundry solutions,” said Kam Kittrell, general manager of Magma’s Design Implementation Business Unit. “Managing power is a key design component at 65 nm, so this new flow reiterates the Magma software’s ability to address a variety of nanometer low-power design challenges.”
Magma-UMC Low-Power Reference Flow: Timing Closure without Iterations
The Magma-UMC RTL-to-GDSII low-power reference flow includes required scripts and documentation to enable Magma users to ramp up to UMC’s advanced 65-nm low-power process technology and deliver silicon quickly. The reference flow delivers complete timing closure without iterations. A multiple-power domain is used to create different voltage domains with designated purposes, including reducing leakage current and reducing chip power consumption while meeting timing requirements. The reference flow also provides MTCMOS power switch insertion and placement for implementing a switched domain, automatic checking and insertion of level shifters and isolation cells to the right locations in a domain, retention of flip-flops and latches in the domain which can be powered down, and always-on buffer insertion for connecting to a secondary power source. In addition, Magma’s advanced placement engines complete all the standard-cell placement in the design using features such as comprehensive congestion analysis and timing-driven placement.
Magma’s clock tree synthesis constructs a minimum-skew clock tree. With the GUI clock-tree browser, users can monitor the clock tree implementation during the flow and can select the correct clock tree structures for their design. After clock tree synthesis is completed, Magma’s advanced routing engines complete the routing, including signal and power routing, based on the user’s specified routing rules. With Magma’s integrated IC implementation solution and its unified data structure as the basis for the reference flow, UMC and Magma customers can deliver high-quality results in terms of timing, area, power, signal integrity and reliability while minimizing the design cycle.
Availability
Please contact your UMC customer service representative to gain access to the reference flow kit. Customers can also obtain the kit by visiting Magma Design Automation on the Web at www.magma-da.com/UMCMagmaReferenceFlow.html. Included with the kit is a summary document describing the flow, run scripts, a tutorial design, design rule Volcano™ and test case results.
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