CIMdata PLM Industry Summary Online Archive

8 December 2008

Implementation Investments

STARC to Deploy Synopsys IC Compiler's Zroute and Clock Mesh Technologies in STARCAD-CEL

Synopsys, Inc. announced that Semiconductor Technology and Academic Research Center (STARC) successfully evaluated Zroute and Clock Mesh, two new technologies found in the latest release of IC Compiler, Synopsys' physical implementation solution. With its unique architecture, Zroute delivers faster runtimes while improving quality of results in timing, area and manufacturability. Clock Mesh targets high-performance designs where tightly controlling clock skew is critical. After successfully evaluating the Zroute and Clock Mesh technologies, STARC is preparing them for deployment in STARCAD-CEL version 3.0. Scheduled for release in the first quarter of 2009, STARCAD-CEL v3.0 will help enable designers of complex, high-performance chips at advanced process nodes to meet their design goals.

"Our objective at STARC is to evaluate and include the latest technology advances in our reference flows so that member companies can achieve leading-edge performance goals," says Nobuyuki Nishiguchi, vice president and general manager, development department 1 at STARC. "In early evaluations of Zroute we saw significant improvements in routing such as up to 3.5X faster runtime and up to 20 percent reduction in via count. With Clock Mesh, we estimated lower skew and higher immunity to on-chip variation, both critical at 45 nanometers and below. And, as part of the IC Compiler 2008.09 release, Zroute and Clock Mesh are very easy to adopt in STARCAD-CEL v3.0."

Zroute's architecture includes advanced routing algorithms and concurrent DFM optimization for an efficient trade-off between manufacturability and the traditional design goals of timing, area, power and signal integrity. In addition, Zroute's native multi-threading support is designed to take advantage of the latest multi-core computing systems to deliver near-linear scalability of runtimes. For designs at advanced process nodes, Clock Mesh generates a clock network that offers superior tolerance to variation due to the high redundancy stemming from its mesh architecture. Additionally, Clock Mesh achieves significant total clock skew reduction, helping enable the highest possible clock frequency, which is key for high-performance designs.

Zroute and Clock Mesh are available in the recently announced 2008.09 release of IC Compiler. This release provides faster runtimes across the board, leading to a 2X to 3X speed-up in overall turnaround time. The 2008.09 release also introduced new technologies such as enhanced design for manufacturability (DFM), lower power and signoff-quality incremental design-rule checking, all of which speed up design closure and improve Quality of Results (QoR).

"We are seeing strong demand by customers worldwide for IC Compiler's 2X speed-up and new technologies in 2008.09 release," said Antun Domic, senior vice president and general manager, Synopsys Implementation Group. "Our long-term collaboration with STARC allows us to continuously deliver the most advanced capabilities to its member companies through STARC's widely used design methodologies. We look forward to deploying Zroute and Clock Mesh, two of our latest technology advances, in STARCAD-CEL v3.0."

STARC is a research consortium of major Japanese semiconductor companies developing leading-edge system-on-chip (SoC) design methodologies.

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