CIMdata PLM Industry Summary Online Archive
11 December 2008
Product News
Mentor Graphics Olympus-SoC Place-and-Route System Qualifies for TSMC 40nm Processes
Mentor Graphics Corporation announced the qualification and immediate availability of its Olympus-SoC™ place-and-route system for chip designs targeting TSMC's 40nm process. These include the efficient 40nm (LP) process for handheld and wireless devices, and the 40nm General Purpose (G) for performance-oriented CPU, GPU, game consoles and networking devices. Olympus-SoC provides a multi-corner, multi-mode driven IC implementation platform that concurrently optimizes timing, power, signal integrity, and manufacturing variability.
“We worked with Mentor Graphics to qualify Olympus-SoC for our 40nm process,” said S.T. Juang, senior director of design infrastructure marketing at TSMC. “We are looking for a place and route system that can meet our requirements and pass our qualification process. All our requirements were met and we expect designers to benefit as they move to TSMC’s most advanced production process.”
In addition to being qualified by fulfilling TSMC’s 40nm process requirements, Mentor’s Olympus-SoC place-and-route system concurrently analyzes and optimizes for variations in process corners, manufacturing, and design modes. Based on patented multi-corner, multi-mode technology and an ultra-compact data model, it comprehensively addresses the performance, capacity, time-to-market, and variability challenges occurring at the leading-edge process nodes. Product highlights include adaptive variability engine, multi-corner multi-mode clock tree synthesis, DFM-driven routing, embedded signoff quality timing engine, multi-corner multi-mode signal integrity (SI), and advanced chip assembly capabilities. In addition, the Olympus-SoC system now provides task-oriented parallelism technology that allows timing analysis and optimization tasks to run in parallel to deliver up to seven times improvement in timing analysis run times, and up to four times improvement in design closure times using eight CPU cores. The solution is proven with multiple tapeouts in various application segments.
“TSMC is a critical partner for Mentor Graphics, and we’ve had great success working together to provide the most advanced solutions for physical verification, DFM, and DFT technologies, now qualified for Reference Flow 9.0,” said Joseph Sawicki, vice president and general manager for the design-to-silicon division at Mentor Graphics. “The addition of our Olympus-SoC system completes Mentor’s design-to-silicon flow for TSMC customers, giving them the most complete, robust and production proven IC implementation solution available.”
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