CIMdata PLM Industry Summary Online Archive
12 February 2008
Implementation Investments
LG Electronics Increases Quality of HDTV Chip Using Synopsys Test Solution
Synopsys, Inc. announced that LG Electronics, Inc. has deployed Synopsys' DFT MAX scan compression solution to significantly increase test quality for a 65-nanometer (nm) HDTV design. DFT MAX automatically implements scan compression on-chip which can reduce the amount of data required to test each manufactured part by 95 percent or more. Reducing test data volume enables more types of deep sub-micron (DSM) tests to be stored in tester memory, resulting in improved quality of production testing and lower testing costs. Data volume reduction also eliminates the need for costly investments to update the automatic test equipment (ATE) infrastructure.
"We outsource much of our production testing to specialty firms that use low-cost ATEs," said Woo-Hyun Paik, vice president of LG Electronics, System IC Business Unit. "Without scan compression, only a fraction of our DSM test patterns can be loaded at one time on these testers, and reloading patterns into memory during full-scale production testing is costly in terms of both time and money. Using DFT MAX to reduce test data volume for our new HDTV chip allowed us to apply all the test patterns at one time and take full advantage of the higher test quality possible with DSM tests."
Standard stuck-at test patterns are ineffective in detecting timing-sensitive manufacturing defects at 0.13-micron geometries and below, so many Synopsys customers are now using advanced DSM tests to target these defects during production testing. To achieve very high test quality at LG Electronics, designers use the Synopsys TetraMAX® automatic test pattern generation (ATPG) solution to generate a combination of transition delay tests, bridging tests, and path delay tests. However, applying all these DSM tests on their large HDTV design would have exceeded the memory capacity of the production testers had they not also used DFT MAX to implement on-chip scan compression. DFT MAX integrates seamlessly within Synopsys' Galaxy™ Design Platform to automatically implement compression which can reduce test data volume and test execution time by 95 percent or more, with low area overhead and virtually no impact on design timing.
"There is a growing need among semiconductor manufacturers to reduce test data volume to make room in memory for the ultra-high-quality test data generated using the latest advances in ATPG technology for detecting subtle nanometer defects," said Gal Hasson, senior director of Synthesis and Test Marketing at Synopsys. "With Synopsys' Galaxy test solution, designers can easily meet their test quality goals while preserving their investments in ATE infrastructure. DFT MAX not only delivers push-button test data compression, but also is integrated with Synopsys' Design Compiler® synthesis, PrimeTime® sign-off, Formality® formal verification, and IC Compiler physical implementation solutions to speed time-to-results and help ensure design predictability."
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