CIMdata PLM Industry Summary Online Archive
20 February 2008
Implementation Investments
Berkeley Design Automation Analog FastSPICE™ Selected by Next-Generation Japanese Supercomputer Project for 45nm Verification
Berkeley Design Automation Inc., provider of Precision Circuit Analysis™ technology for advanced analog and RF integrated circuits (ICs), announced that the company's Analog FastSPICE™ circuit simulator has been selected for complex analog and mixed-signal block verification in a next-generation 45nm supercomputer chip developed by the University of Tokyo and RIKEN.
“Berkeley Design Automation verification tools are critical to the success of our next generation 45nm supercomputer project,” said Professor Takashi Ikegami of the University of Tokyo. “Analog FastSPICE delivered accuracy that is as good or better than traditional SPICE 5x-10x faster on our complex analog and mixed-signal blocks. Since we cannot rely on digital fastSPICE approximations for these designs, Analog FastSPICE enables us to perform verification tasks that were previously impossible."
“Analog FastSPICE is allowing us to verify our analog and mixed-signal blocks faster than we thought possible,” said Duraid Madina, also of the University of Tokyo. “Analog FastSPICE is not only faster and more accurate than our other SPICE tools – it is faster than digital fastSPICE tools that cannot handle our mixed-signal designs. In our testing, Analog FastSPICE was often 10x faster than the best traditional SPICE, while giving identical results. We never observed a difference greater than 0.15%.”
Berkeley Design Automation tools include Analog FastSPICE™ circuit simulation, RF FastSPICE™ periodic analyzer, and PLL Noise Analyzer™. The company guarantees identical waveforms to the leading "golden" SPICE simulators down to noise floor (typically 0.1% or less) while delivering 5x-10x higher performance and 5x-10x higher capacity. It achieves this by using advanced algorithms and numerical analysis techniques to rapidly solve the full-circuit matrix and the original device equations without any shortcuts that could compromise accuracy.
Design teams from top-10 semiconductor companies to leading startups use Berkeley Design Automation tools to solve big analog/RF verification problems. Typical applications include characterizing complex blocks (e.g., PLLs, ADCs, DC:DC converters, PHYs, Tx/Rx chains) and running performance simulation of full circuits (e.g., wireless transceivers, wireline transceivers, high-speed I/O macros, memories, microcontrollers, data converters, and power converters).
“We are delighted and honored to be selected by the consortium as the circuit simulator of choice for the 45nm MDGRAPE-4 supercomputing chip,” said Ravi Subramanian, president and CEO of Berkeley Design Automation. “Our selection by this distinguished team is once again proof that Berkeley Design Automation’s Precision Circuit Analysis™ technology is essential for success in nanometer analog/RF design.”
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