CIMdata PLM Industry Summary Online Archive
13 April 2009
Product News
Magma's New Talus Design Delivers Fastest Design Turnaround and Superior Results for Advanced Chips
Magma® Design Automation Inc. announced the availability of an upgraded version of Talus® Design, Magma's full-chip synthesis product for advanced integrated circuits. The new release includes an enhanced timing optimization engine, improved memory efficiency and advanced productivity improvements such as out-of-the-box usability, advanced scripting language for more flexibility, and support for leading third-party design-for-test (DFT) products. The combination of Talus Design with Talus Vortex provides a complete RTL-to-GDSII solution for implementing the most advanced designs, enabling designers to fully optimize and accurately predict final chip performance early in the design cycle and minimize design iterations.
Sigma Design, an early adopter of Talus Design, has used the product in a number of recent successful high-performance tape-outs.
"Managing, importing and exporting the various databases and files required for each tool in traditional flows is a complex, time-consuming task and can introduce errors into the design," said Jacques Martinella, vice president of Engineering of Sigma Design. "With Magma's RTL-to-GDSII flow, all the design data is captured in a single binary file called a Volcano™. This simplifies data management and improves our overall productivity. The tight integration of this system and the recent enhancements to Talus Design and Talus Vortex were key to Sigma's decision to standardize on the Magma flow."
"The technical challenges of nanometer design have been compounded by economic pressures to create more complex and differentiated chips in less time and with fewer engineering resources," said Premal Buch, general manager of Magma's Design Implementation Business Unit. "By leveraging the same optimization and analysis engines available in the Talus Vortex physical design environment, Talus Design offers designers the high degree of predictability and improved productivity needed to meet tough performance and turnaround-time requirements".
Talus Design: Fast, High-Capacity RTL and DFT Synthesis
Leveraging the high capacity of Magma's unified data model, and with improved memory efficiency over earlier releases, Talus Design synthesizes multimillion-instance RTL designs without hierarchical partitioning or guard-band-related timing constraints. The capacity restrictions of traditional tools require designers to break up large designs into numerous blocks and limit the designer's ability to optimize the design. Talus Design's high capacity enables entire chips or just a few large blocks to be synthesized in a single pass and delivers superior optimization results. An incremental elaboration capability allows small changes to the design's RTL to be propagated into the implementation flow without the manual process of recompiling the entire design. Elaboration engine improvements now provide concurrent language support for VHDL, Verilog and System Verilog.
To improve testability of the design, Talus Design supports top-down and bottom-up hierarchical scan insertion throughout the synthesis and physical design flow. Talus Design has a comprehensive and configurable DFT flow check engine that allows the user to analyze and debug testability issues. With these capabilities and proven interoperability with third-party test solutions, Talus Design provides comprehensive DFT support.
Talus Design and Talus Vortex: A Single Solution for Improved Predictability and Productivity
The complete Magma Talus flow eliminates timing mismatches between synthesis and physical design because it's built on a unified data model and uses a single static timing analyzer throughout the Talus RTL-to-GDSII flow. Talus Design enables logic designers to experiment at early stages of the design process with incomplete data to improve RTL and timing constraints. These early optimizations eliminate time-consuming iterations toward the end of the design cycle and allow the logic designer to hand off the design to the implementation team with a very high degree of confidence that it will achieve design closure.
Using a single Volcano database, designers benefit from a comprehensive self-documenting repository for all design information, ensuring an error-free method of exchanging information between logical and physical design teams. Magma Tcl scripting is also available throughout the tool flow to help automate and simplify complex tasks, delivering a powerful, productive environment that enables designers to meet the technical and market challenges of today's semiconductor designs.
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