CIMdata PLM Industry Summary Online Archive
30 April 2009
Implementation Investments
Verivue Deploys VMM and Synopsys VCS Solution for Verification of Scalable Media Distribution Switch
Synopsys, Inc. announced that Verivue, Inc. has standardized on the VMM verification methodology and VCS® functional verification solution, both key components of Synopsys' Discovery™ Verification Platform, for the verification of their flagship product, the MDX 9000 Series Media Distribution Switch. The VMM-based approach allows Verivue to implement a transaction-based verification methodology that provides reusable test environments for higher test coverage, ease-of-use and scalability from block to system-level. The combination of the VCS solution and VMM enables faster turn-around with accelerated compile times and optimized performance for system designs, contributing to a productivity boost of up to 4x over traditional approaches.
"The MDX 9000 system is architected to meet the media delivery requirements of cable operators, carriers and content delivery network providers," said Robert Ryan, vice president of Hardware Development at Verivue, Inc. "It's an extremely complex product with a large amount of functionality built into the hardware. However, VMM enabled us to quickly build testbenches to verify functional blocks, FPGAs and board netlists. VMM allowed us to create suites of pseudo-random, self-checking tests for each testbench and, as we developed the system, run regression tests to verify that it functioned as designed."
A major benefit of VMM-based verification environments is verification reuse. With VMM, Verivue is able to create fifteen "plug-and-play" transaction models that can generate large volumes of data. Engineers are able to boot the entire system as soon as the hardware becomes available. Additionally, the VMM Applications, such as Register Abstraction Layer (RAL), speed up and simplify verification.
"With hundreds of successful deployments in highly complex verification environments, VMM is the most widely used verification methodology," said Swami Venkat, senior director of Marketing in the Verification Group at Synopsys. "Engineers using VMM and VMM Applications consistently achieve higher quality verification results and greater verification productivity, as evidenced in a large number of VMM user papers and tape-outs. Synopsys continues to invest in verification methodology innovations with new technologies such as the VMM for Low Power to address complex functional verification challenges."
About VMM
The VMM methodology enables chip development teams to use SystemVerilog to create comprehensive verification environments using transaction-level, coverage-driven, constrained-random and assertion-based techniques, and specifies library building blocks for interoperable verification components. The VMM methodology has been proven in production by hundreds of SoC, system, FPGA and silicon IP verification teams around the world. In addition to the VMM base class library and applications, a variety of useful resources that help improve productivity for both new and existing VMM users are available at http://www.vmmcentral.org. The VMM for Low Power (VMM-LP) extends the VMM methodology for designs that employ aggressive power management techniques; the VMM-LP book is available for download at http://www.vmmcentral.org/vmmlp.
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