CIMdata PLM Industry Summary Online Archive
9 June 2009
Implementation Investments
Faraday Technology Reduces IC Power Consumption and Cuts Design Time by 20 Percent Using Cadence Low-Power Solution
Cadence Design Systems, Inc. announced that Faraday Technology Corporation has utilized the Common Power Format (CPF) enabled Cadence® Low-Power Solution to successfully tape out more than 20 low-power chip designs.
As a leading ASIC services company, Faraday has seen customers’ designs increasing in complexity. This has resulted in a 3X average increase of design sizes over the past year. However, by using an integrated methodology based on the CPF-enabled Cadence Low-Power Solution, as well as adopting a platform-based design approach, Faraday was able to take on the increased design complexity and improve average design time by 20 percent over the course of the year. This trend was demonstrated consistently over a span of more than 20 low-power designs.
“The Cadence Low-Power Solution provides us with exactly what we need to produce a consistent and reliable flow for taping out low-power designs,” said Kun-Cheng Wu, associate vice president of SoC & SiP Development and Service of Faraday Technology Corporation. “Leveraging the advanced technology in the Cadence Low-Power Solution, we now have a proven methodology providing the best power optimization design services for our customers worldwide.”
“By being able to complete much larger designs in less time, with the added complexity of advanced low-power features, Faraday has shown that using the Cadence Low-Power Solution to optimize chip power consumption is the best way to go,” said Steve Carlson, vice president of product marketing at Cadence Design Systems. “The phenomenal productivity results are a tribute to the union of great engineering and great engineering solutions.”
The Cadence Low-Power Solution features critical technologies for power-efficient design, including the Encounter® Digital Implementation System and Conformal Low-Power. By using the Encounter Digital Implementation System for physical implementation, Faraday’s design teams have access to native power domain support and integrated power signoff through Encounter Power System. In addition, Conformal Low-Power provides Faraday with pre-layout and post-layout functional and structural checking, ensuring correctness of the final silicon. Encounter Digital Implementation System and Conformal-LP are integral parts of the CPF-enabled Cadence Low-Power Solution.
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