CIMdata PLM Industry Summary Online Archive
15 July 2009
Events News
Cadence Showcases Comprehensive Design Solutions at 46th DAC
Cadence Design Systems, Inc. will showcase a variety of solutions highlighting the company’s technology leadership at the 46th annual Design Automation Conference (DAC), July 26-31 in San Francisco. In collaboration with customers and ecosystem partners, Cadence will demonstrate these innovations in multiple venues, emphasizing the depth and breadth of its focus on methodologies and solutions that support design projects in both leading edge and mainstream process technologies.
“Over the past year, Cadence has led the investment in new technologies that are vital to the continued success of our customers, and to the electronics industry,” said Lip-Bu Tan, president and CEO of Cadence Design Systems. “As the industry’s premier conference, DAC provides Cadence with a valuable opportunity to share our latest advances in core technologies and solutions with customers.”
The latest developments in system solutions, low-power, advanced node, mixed-signal, and enterprise verification will be shown in the Cadence demo suites in booth #3751:
• SystemC TLM-Driven Design and Verification Flow - The RTL design paradigm is 20 years old. Cadence is driving a SystemC transaction-level modeling (TLM) solution with breakthrough technologies including the Cadence C-to-Silicon Compiler and Incisive® Software Extensions, as well as SystemC TLM extensions;
• Low Power for All: Reduce Power While Reducing Risk - The legacy challenges of increased risk and design effort are squarely addressed by this holistic, highly automated, and predictable environment and methodology for design, chip planning, verification, and implementation of digital and mixed-signal designs, as well as professional design services.
• Accelerate Your Advanced Node Design - Accelerate leading-edge designs with complete, integrated design-for-manufacturing (DFM) solutions. Cadence provides a consistent and converging flow across the Encounter® Digital Implementation System and Virtuoso® Custom Implementation solutions addressing DFM and variability effects, including lithography, CMP, stress and process variation, while providing significant productivity gains over traditional DFM closure solutions.
• It’s a Mixed-Signal World – Seamlessly integrate analog and digital design environments. Half of all SoC respins are caused by inefficiencies in mixed-signal integration and verification. The Cadence mixed-signal solution provides a proven design, implementation, and verification methodology for IC, SoC, and SiP designs with complex analog and digital design challenges.
• Enterprise Verification: Reducing Risk with Comprehensive Metrics - The Cadence Enterprise Verification solution provides a predictable verification process from block to chip to system, increasing productivity while improving design quality. It has the breadth and depth to handle the complete functional verification needs of today’s designs.
Collaboration across the electronics industry is essential to ensure customer success. In booth #4300, attendees can learn more about how industry leaders ARM, Cadence and TSMC are working together to facilitate interoperability and optimize handoffs throughout the entire design chain. Customers and partners will share success stories of collaborative efforts and attendees will be invited to listen to panel discussions on current design topics.
This year, Cadence will participate in several additional venues, including:
• ChipEstimate.com booth #1100
• OVM World booth #3450
• TSMC Open Innovation Platform booth #822
• Si2 booth #1400
• IBM booth #4311
To learn more about Cadence at DAC this year, and to register for a Cadence event, please visit us at http://www.cadence.com/dac2009.
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