CIMdata PLM Industry Summary Online Archive
15 January 2009
Product News
STARC Qualifies Cadence Encounter Conformal Constraint Designer for STARCAD-CEL Flow
Cadence Design Systems, Inc. announced that the Semiconductor Technology Academic Research Center (STARC) in Japan has qualified the Cadence® Encounter® Conformal® Constraint Designer for use in the STARCAD-CEL design flow for advanced semiconductor design. The qualification demonstrates that Encounter Conformal Constraint Designer has delivered production-quality results and provides a solution for the various requirements of multiple STARC member companies.
"Designers spend a lot of time manually assembling chip-level design constraints, which can be tedious and error prone,” said Nobuyuki Nishiguchi, Vice President and General Manager, Development Department 1 at STARC. “With the Cadence Encounter Conformal Constraint Designer, one can quickly integrate and optimize block-level constraints, while using what-if analysis to create effective chip-level constraints. This results in significantly improved productivity and design quality.”
To qualify, Encounter Conformal Constraint Designer passed a rigorous test involving more than 100 individual evaluation items. By qualifying for the STARCAD-CEL flow, Encounter Conformal Constraint Designer becomes an integral part of an advanced-node methodology widely deployed in Japanese companies developing large-scale, complex digital designs utilizing advanced low power and design-for-manufacturing techniques.
Encounter Conformal Constraint Designer’s template generation and check features are already qualified by STARC and adopted in the flow. The addition of SDC integration features in Conformal Constraint Designer completes the constraint generation flow for STARC member companies, improving time to tapeout and quality of results compared to manual debugging.
“Cadence Encounter Conformal Constraint Designer delivers a robust, production-quality flow for constraint management that reduces time to tapeout and improves the quality of results for complex SoCs,” said Andy Lin, VP of R&D, Formal Verification at Cadence Design Systems. “Fundamentally, this means STARC member companies can reduce the risk of production problems, allowing for a faster ramp to volume production at advanced process nodes.”
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