CIMdata PLM Industry Summary Online Archive

20 July 2009

Implementation Investments

XMOS Uses Magma Talus 1.1 to Improve Quality of Results On New XS1-L1 Event Driven Processor

Magma® Design Automation Inc. announced that XMOS, a leader in event driven processors™, taped out its recently announced XS1-L1 XCore™ using the Talus® 1.1 IC implementation system. XMOS upgraded to the latest version of the Magma software after early testing showed improvements in the closure of their XCore processor design.

"We benchmarked an early release of Talus 1.1 during the XS1 development program," said Mark Lippett, vice president of engineering at XMOS. "Improvements in the routing algorithms led us to migrate to the Talus 1.1 release for our production tapeout."

The XS1-L family provides embedded software developers with an energy-efficient, scalable, multi-core solution. It enables complete systems that combine interface, DSP and control functions to be built entirely in software. Each XS1-L XCore contains a 32-bit processor and operates up to 400MIPS. XCore power consumption is below 500 microwatts in sleep mode and 20 milliwatts in standby with active power adding under 450 microwatts/MHz. The event-driven architecture, together with XMOS' programming tools, enables XCores to switch automatically between standby and active modes, saving up to 90 percent of energy in low duty-cycle applications. The XS1-L1 is built on a 65-nanometer process. Samples are available now from www.xmos.com.

"Like XMOS, many of our other customers are implementing very complex chips and need a powerful, fast, high-quality chip design system that is also easy to use," said Premal Buch, general manager of Magma's Design Implementation Business Unit. "Talus 1.1 features simplified flows with fewer commands and still provides improved performance, timing closure and power optimization. XMOS' ability to deploy Talus 1.1 quickly to meet their design requirements demonstrates the advantages of Magma's COre technology."

Talus COre Technology

The heart of the improvements in Talus 1.1 is its Concurrent Optimizing Routing Engine (COre) technology. At advanced geometries, complex resistance effects, increased via resistance and crosstalk can create a large timing disconnect between placed gates and final routing. Talus COre focuses on applying the full scope of timing optimization incrementally during routing. Every aspect of the routing algorithms -- from topology generation to layer assignment, track assignment and design rule checking (DRC) violation cleanup -- is timing and crosstalk aware. This allows the design to converge faster and eliminates post-route timing surprises. Talus COre is coupled with Talus' Standard Delay Format (SDF)-based optimization to remove the need for manual engineering change orders (ECOs) to close timing.

About XMOS

XMOS is a leader in event-driven processors for digital electronics. XMOS event-driven processors are high-performance, predictable, processors. They allow complete systems to be implemented in software using interface, DSP and control code. XMOS is an enabling technology for the Open Source Hardware community. Designs, including USB, Ethernet, and SD-RAM controllers are available in an ever-expanding library of open source code. Free to download, the XMOS development tools are supported by a vibrant community of digital designers and software engineers.

XMOS has corporate offices in Sunnyvale, Calif., Bristol, United Kingdom and Chennai, India and sales offices and representatives across the world.

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