CIMdata PLM Industry Summary Online Archive
6 January 2010
Implementation Investments
Mentor Graphics Supports the Canon India Design Centre’s Migration to OVM
Mentor Graphics Corporation announced that the Canon India Design Centre has successfully deployed the Questa® advanced verification platform with SystemVerilog as a next-generation HVL and Open Verification Methodology (OVM)-based verification environment.
The Canon India Design Centre chose the Questa advanced verification platform, combined with the OVM, to ensure the highest level of modularity, productivity and reuse for the verification of Canon India’s complex and highly compute-intensive integrated circuit (IC) designs. In particular, the Canon India Design Centre verification team used SystemVerilog with OVM for verifying multi-layered communication IP.
“The OVM defines the concept of ‘object oriented’ for verification environment in a systematic way,” said Sunil Kashide, Verification head at the Canon India Design Centre. “We were able to define and build the verification architecture much more robust and modular. Mentor India has given extensive support in understanding and exercising the different concepts. With OVM, we could reduce the overall timeline by bringing parallelism into execution.”
“Mentor Graphics’ team has provided us extended support during the evaluation phase,” said Dhanaji Kamble, Design Centre head. “We could successfully build the domain expertise and boost team confidence for the next-generation verification methodology.”
“The OVM was developed to deliver ready-to-use, reusable, and scalable testbench components within a proven, repeatable methodology,” said John Lenyo, general manager of Mentor’s Functional Verification division. “The combination of industry-leading SystemVerilog support and OVM-specific debug capabilities in the Questa functional verification environment has helped customers like Canon India quickly get successful results in real projects.”
About the Open Verification Methodology (OVM)
The OVM is based on the IEEE 1800 SystemVerilog standard and supports design and verification engineers developing advanced verification environments that offer higher levels of integration and portability of Verification IP. The methodology is non-vendor specific and is interoperable with multiple languages and simulators. The OVM is fully open and includes a robust class library and source code that is available for download.
About Canon India
Canon India Private Limited, India's No. 1 Complete Digital Imaging Company, started the software development centre ISDC (India Software Development Centre) in 1999. The ISDC is comprised of multiple divisions, namely SDC (Software Development Centre), CoE (Centre of Excellence) and Design Centre. SDC and CoE are located at Noida and Design Centre is located at Bangalore.
The Design Centre at Bangalore started in 2008 with a vision to focus on VLSI/ASIC Design and Firmware/Software development. The key areas of focus for the ASIC Design group are: IP development, Verification IP Development, SoC (System on Chip) architecture and development, Post-silicon Validation, and FPGA prototyping. The group is well skilled to tape-out the multi-million gate count SoC with 45nm and 65nm technology. The verification team is highly skilled to work in state-of-the-art verification methodologies.
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