CIMdata PLM Industry Summary Online Archive
29 March 2010
Product News
Mentor Graphics and Platform Computing Optimize Use of Veloce Emulation Systems as Shared Resources
Mentor Graphics Corp. announced that they have successfully deployed Platform LSF to optimize the use of Veloce® emulation systems as shared resources. The implementation allows users to maximize utilization and increase emulation return on investment.
For companies that use Veloce emulators as a networked, shared resource, Platform LSF allows them to access multiple Veloce systems and partitions within individual systems without recompiling their designs. This approach is in contrast to other emulators where the design is locked to a specific user partition during compilation. In this scenario, even when a partition becomes ‘free,’ there is no flexibility to run a job on the ‘free’ partition without a full recompile of the design.
In addition, to further leverage Platform LSF and the optimization of Veloce emulation systems, the Veloce Testbench Express (TBX) capabilities can replace the fixed hardware setup of in-circuit emulation with interface transactors. The transaction-based implementation takes the Veloce system from being configured to a single design to a general purpose emulation resource capable of running any design.
Maximize Utilization with Platform LSF and Veloce Platform LSF schedules jobs and establishes priority-based queues. Further, Platform LSF allocates the appropriate Veloce emulation resources to meet the specific verification needs and capacity requirements for verification jobs across multiple projects within a company. This scheduling maximizes the use of the Veloce systems, and is instrumental in supporting transaction-based accelerated verification environments.
To facilitate the optimized chip design and testing environment, both Mentor and Platform Computing added features to their products. The Veloce emulators now provide improved flexibility for multi-user access to available partitions without the need for compilation to a specific partition. Platform Computing added a knowledge base of the various Veloce family systems to be able to optimally queue up and allocate resources for verification jobs of different sizes across multiple projects.
“Our close collaboration with Mentor will empower our mutual customers in systems design and fabrication to maximize their resources and speed the time to market for the latest embedded chip technologies,” said Peter Nichol, general manager, HPC Business Unit, Platform Computing. “The custom-designed Veloce verification platforms that have been integrated with Platform LSF as part of the joint solution ensure a solution that easily allows designers to work on multiple work-load-intensive projects faster.”
“We worked closely with Platform Computing to leverage their expertise and create an environment that approaches ‘cloud emulation,’ ” said Eric Selosse, vice president and general manager, Mentor Emulation Division. “Our customers find that with the infrastructure we now provide, the ROI for their emulation investment is maximized, and they can better address the challenges in verifying their complex SoC designs.”
About the Veloce Platform
The Veloce platform provides MHz performance for embedded software validation, transaction-based verification and traditional in-circuit emulation (ICE). Design and verification teams use Veloce systems as a reconfigurable representation of new system-on-chip designs. As a flexible hardware model of the design, the Veloce system is used to verify SoC hardware and software designs while both are still fluid and prototype chips have not yet been fabricated. With an extensive portfolio of vertical market solutions, the Veloce platform is the platform of choice for multimedia, networking, wireless, and embedded systems applications.
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