CIMdata PLM Industry Summary Online Archive
11 January 2010
Implementation Investments
Agilent Technologies’ RFIC Solutions Software Accelerates Design, Verification of ACCO Semiconductor’s Next-Generation CMOS Power Amplifier
Agilent Technologies Inc. announced that ACCO Semiconductor has selected a comprehensive suite of Agilent’s RFIC design, verification and modeling software for design of its next-generation CMOS power amplifier. This software, used for integrated, mixed-signal RFIC designs, coupled with Agilent’s wireless verification IP portfolio for design and test, enables a streamlined design flow that allows ACCO Semiconductor to drive its design project from initial conception to final product.
“In today’s cellular marketplace, one of the most difficult jobs for an R&D manager is to navigate from product concept to finished product -- a process which, to be successful, typically requires the application of multiple technologies and multiple design flows,” said Ron Das, president and CEO of ACCO Semiconductor. “The entire design chain must be coordinated or it will break, resulting in a missed deadline or market window, significant cost overruns, and lost business. The streamlined flow provided by Agilent’s EDA tools allows us to avoid these hardships and bring our product to market faster.”
A streamlined flow is critical to successful product development and key to eliminating the integration risks that can arise late in the development cycle. Agilent’s streamlined design and verification flow serves as a focal point for all teams involved in product development -- including semiconductor modeling, system architecture, RF design, and prototype validation. It begins with active and passive modeling, using Agilent’s IC-CAP device modeling software and Momentum 3-D planar electromagnetic simulator. The flow then continues into system design using the leading-edge RFIC tools in Agilent’s GoldenGate software, along with Agilent’s wireless verification libraries. Common waveforms and data processing algorithms are used throughout design and measurement to ensure a coherent and efficient prototype verification process.
About GoldenGate
GoldenGate is a trusted simulation, verification and analysis solution for integrated RF circuit design within the Cadence Virtuoso design flow. Its simulation algorithms are optimized for the demands of today’s complex RF circuit design, enabling full characterization of complete transceivers prior to tape-out. GoldenGate is part of Agilent’s RFIC simulation, analysis and verification solution that also includes Momentum for 3-D planar electromagnetic simulation, Ptolemy Wireless Test Benches for system level verification, and the Advanced Design System (ADS) Data Display for advanced data analysis. This suite links the RF system, subsystem, and component-level design and analysis as part of a unique and comprehensive RFIC design flow. GoldenGate is fully compatible with Cadence IC5 and IC6 platforms.
For more information about Agilent’s GoldenGate, go to http://www.agilent.com/find/eesof-goldengate
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