CIMdata PLM Industry Summary Online Archive
28 January 2010
Events News
Synopsys Offers Designers Many Opportunities for Design Success at EDSFair
Synopsys, Inc. announced that more than 1000 design engineers have registered to attend pre-registration-required Synopsys events at the Electronic Design and Solution Fair (EDSFair 2010) in Yokohama, Japan. These numbers represent a significant increase in registration over last year. Through many events including these, Synopsys will provide attendees with opportunities to learn about the latest technology developments in the software to silicon arena. Events include product and solution demonstrations in the booth and suite, customer and Synopsys presentations at the booth theater, technical sessions at Synopsys’ PrimeTime® Special Interest Group (SIG) event and EDSFair Exhibitor Seminar, a panel discussion at the EDSFair Special Stage and support of the IPL Alliance booth, The EDSFair is to be held January 28 to 29 at the Pacifico Yokohama Convention Complex.
“Technical community events such as customer sessions at our booth theater and the EDSFair Special Stage are a valuable way for design engineers to learn about the latest trends in state-of-the-art design technology and share experiences and new ideas with other members of the community,” said Kimio Fujii, president of Nihon Synopsys G.K. “Our customers want to collaborate with us to improve the quality and productivity of their designs. The events provide a mechanism to not only exchange practical and advanced approaches in the design community but also to get end-user feedback that can have high impact on our product development efforts.”
In the Synopsys’ booth (#001), 13 demo tables will showcase Synopsys’ comprehensive solution, including the Galaxy™ Implementation Platform, Discovery™ Verification Platform, Eclypse™ Low Power Solution, Software-to-Silicon verification solution, FPGA and high-level synthesis solutions, DesignWare® IP solutions, manufacturing and TCAD solutions and the Lynx™ Design System. Details on these solutions and the newest technology can been seen in the Synopsys suite. At the theater in the booth, nine major semiconductor and system companies will talk about their advanced design experience using Synopsys tools and solutions. In addition, Synopsys will present three new solutions including Synphony high-level synthesis, the Galaxy Custom Designer™ implementation solution and an optimized solution for 32-/28-nanometer (nm) mobile system-on-chip (SoC) designs. Synopsys will also have 12 technical sessions at the EDSFair Exhibitor Seminar and will host a PrimeTime SIG event to drive an active community for all PrimeTime users and design engineers who want to stay connected with the latest static timing analysis (STA) developments. In a panel discussion at the EDSFair Special Stage, George Zafiropoulos, vice president of Solutions Marketing at Synopsys, will highlight the Eclypse Low Power Solution, which can address the requirements of STRJ (Semiconductor Technology Roadmap committee of Japan) and JEITA (Japan Electronics and Information Technology Industries Association). Furthermore, Synopsys will support the IPL Alliance booth (#302) to contribute interoperability enhancements for process design kits based on the OpenAccess database.
“Collaboration is a great way for the design community to address the increasing challenges of advanced semiconductor design,” continued Fujii. “At EDSFair, several of our customers will share their advanced design experiences using our solutions. Our advanced technologies enable engineers to solve complex design challenges and achieve their time-to-market goals. Some of the technologies that will be discussed include IC Compiler Zroute, multi-corner/multi-mode (MCMM), In-Design Rail Analysis and Physical Verification, the VMM-LP low power verification methodology, PrimeTime advanced on-chip variation and HAPS high-performance ASIC rapid prototyping capabilities.”
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