CIMdata PLM Industry Summary Online Archive
2 May 2011
Product News
Synopsys and HHNEC Announce the Availability of Low Power Reference Flow 3.0
Synopsys, Inc. and Shanghai Hua Hong NEC Electronics Company, Ltd (HHNEC), one of Mainland China's leaders in the field of IC foundry service, announced the availability of the 130-nanomter (nm) reference flow, version 3.0. The reference flow, a result of collaboration between Synopsys and HHNEC, adds the Synopsys Eclypse™ Low Power Solution to previous reference flows available to designers. Designers have immediate access to an optimized path to HHNEC silicon at 130-nm, enabling them to meet their project and cost requirements.
Reference Flow 3.0 includes implementation and verification capabilities of Synopsys' Galaxy™ Implementation and Discovery™ Verification platforms to enable engineers to deploy advanced low power techniques. Capabilities added for reference flow 3.0 include Synopsys’ Formality™ solution for low power equivalence checking, MVRC for static rule checking, Power Compiler™ tool for power optimization, and VCS™ with MVSIM for multi-voltage simulation.
The reference design flow was validated using HHNEC’s in-house-developed cell library, SRAM, and IO Library for 130-nm. A full low power cell library from HHNEC is ready for customer use. The test chip used to validate the reference flow features a multi-supply and multi-voltage design.
“Hua Hong NEC ’s 130-nanometer non-volatile memory process requires a flow that addresses leakage power to meet our customers’ need for power efficient designs,” said Wang Nan, design service director at HHNEC. “We worked closely with Synopsys to deliver a solution that enables mutual customers to leverage Synopsys’s strength in low power design and our manufacturing expertise.
Availability
The HHNEC-Synopsys Reference Flow 3.0 is available now from HHNEC; for more information, please contact your HHNEC account manager (ds@hhnec.com).
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