CIMdata PLM Industry Summary Online Archive
15 February 2011
Product News
Si2’s Low Power Coalition Releases Common Power Format Standard Version 2.0
Today the Silicon Integration Initiative (Si2) announced release of the Common Power Format (CPF) Version 2.0, incorporating major enhancements to the widely adopted low-power intent
The enhancements and new capabilities in CPF 2.0 consist of two major categories. Guided by the Si2 Interoperability Guide for Power Format Standards released in March 2010, the release of CPF 2.0 includes the following features to improve interoperability with IEEE 1801-2009: the new concept of generic mode to model either a power mode or a functional mode; the improved hierarchical flow to support output and bi-directional virtual ports; the support of pg_type in supply net connection; more flexibility in modeling different types of isolation, level shifter and retention logic. In addition, based on contributions from member companies and collaboration with the LPC Modeling Working Group, the following extensions are included in the CPF 2.0 release: the new concept of power design to further improve hierarchical low-power design flow; the improvements in macro-modeling of mixed-signal IP with low power features; simplified modeling methodology for I/O pads with complex power management logic; added flexibility to control the corruption semantics for power aware RTL simulation; and extensions to model new low power standard cells such as multi-bit isolation and level-shifter cells, multi-stage level-shifters, etc.
“Interoperability between power-intent file format commands and concepts is important for end user and tool developers alike. Power affects the entire verification and design flow. IBM and our OEM customers use a myriad of EDA tools in these flows for their design and verification. Easy translation between power formats eases the burden of parsing and modeling the information. Designers can more easily convert from one format to the other to run tools that support one of the formats,” says Leon Stok, Vice President, Electronic Design Automation Technologies, IBM Systems and Technology Group.
“Along with the practical additions to the language based on four years of use in the industry, another important addition to CPF 2.0 is the combination of functional modes with power modes of a design,” continues Stok. “This allows a designer to consider power management as an integral part of the function. Modeling these two pieces of information together as a single concept allows a design tool to understand the tradeoffs between power and function - something that design teams struggle with today.”
“The Cadence CPF-based low-power solution — with technologies spanning across our System Realization, SoC Realization and Silicon Realization product lines — delivers the most mature flow to address the challenges of modern advanced low-power designs,” said Charlie Huang, senior vice president and chief strategy officer at Cadence Design Systems. “Si2’s continuous advancements of CPFenable Cadenceto develop new capabilities in our low-power solution to help our customers meet the requirements for future advanced low-power designs.”
“Improvement of interoperability between CPF and IEEE 1801 stands out in CPF 2.0,” says Prabhu Krishnamurthy, Senior Director, Design Implementation, LSI. “Semantic equivalence to the 1801 standard is achieved by adding new options to commands to specify isolation, level shifter and retention rules. Significantly, the addition of generic mode in CPF makes it compatible with power states in 1801. These changes will help ASIC companies like LSI to more easily use mixed flows with best-in-class tools from different vendors thus enabling better quality and turnaround times.”
CPF 2.0 is available for download at: http://www.si2.org/?page=811.
Background
CPF is a Tcl-based format used to capture the power intent of a design. CPF complements the RTL and/or netlist description of the design allowing existing golden RTL/netlist blocks to be used without modification. CPF has achieved wide acceptance in EDA tools in end-user tool flows, and enjoys a record of numerous completed chip tape-outs with subsequent testimonials, and adoption into leading foundry reference flows.
The CPF standard was approved and made publicly available in March of 2007. CPF is supported by many adoption aids and tools, all available from Si2: a CPF tutorial (in both English and Mandarin), a CPF Parser software, the CPF Pocket Guide, an LPC Glossary, and an Interoperability Guide. CPF is supported not only by the Low Power Coalition, but also the Power Forward Initiative, http://www.powerforward.org.
About the Low Power Coalition (LPC)
The Low-Power Coalition (LPC) is delivering enhanced capabilities in low-power Integrated Circuit (IC) design flows in particular relating to specifications of low-power design intent, architectural tradeoffs, logical/physical implementation, design verification and testability. Member companies are: Apache Design Solutions, ARM, Atrenta, Cadence Design Systems, Calypto Design Systems, Entasys, IBM, LSI, and Magma Design Automation. For further information on the Low Power Coalition, see http://www.si2.org/?page=1235.
Become a member of the CIMdata PLM Community to receive your daily PLM news and much more.
Tell us what you think of the CIMdata Newsletter. Send your feedback.
CIMdata is committed to your privacy. Your personal information will never be sold or shared outside of CIMdata without your express permission.