CIMdata PLM Industry Summary Online Archive

19 March 2012

Events News

Cadence to Keynote, Present Papers at ISQED

Tom Beckley, senior vice president of Research and Development, Custom IC and Signoff, Silicon Realization Group at Cadence Design Systems, Inc, will deliver a keynote on advanced node chip design at the International Symposium on Quality Electronic Design (ISQED). In addition, Cadence engineers will participate in two paper presentations at the conference.

When:

March 19 to March 21

Where:

Techmart Center, Santa Clara, Calif.

What:

Beckley, who leads R&D for Cadence custom IC and signoff technology, will deliver a keynote on, “Taming the Challenges in Advanced Node Design” at 8:15 a.m. March 20.

At 2:30 p.m. March 20, Cadence will join representatives of the IBM Semiconductor Research and Development Center to deliver a paper titled, “Understanding, Modeling, and Detecting Pooling Hotspots in Copper CMP.”

At 5:30 p.m. March 20, Sachin Shrivastava and Harindranath Parameswaran from Cadence will deliver a paper titled, “Efficient Reduction Techniques for Statistical Model Generation of Standard Cells.”

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