CIMdata PLM Industry Summary Online Archive

22 May 2012

Events News

Cadence Demonstrates Collaboration, Innovation and Technology Leadership at 49th DAC

Cadence Design Systems will demonstrate the latest innovations and solutions to key technology challenges, solved in collaboration with customers and partners, at DAC 2012.

WHERE: DAC 2012 will take place at the Moscone Convention Center in San Francisco

WHEN: Sunday, June 3 through Thursday, June 7, 2012

WHAT: Connect with Cadence and its partners at DAC for a variety of live presentations in Booth 1930, featuring real-world solutions to help design teams innovate and succeed with the highest quality silicon, system-on-chip devices, and complete systems.

Cadence demo suites feature the latest advantages in mixed-signal, low-power, RTL-to-GDSII, custom/analog, functional verification, verification IP, system development and HW/SW integration, high-level synthesis, signoff analysis, and PCB and packaging. Demo Suites Schedule

Cadence will once again host the EDA360 Theater featuring more than 40 presentations from Cadence, its partners, and customers who will share their experiences and results.

Cadence technologists will discuss industry trends and technology advancements at a wide variety of sessions at DAC 2012. See complete schedule.

Collaboration across the electronics industry is necessary to address the most advanced technology challenges. This year, Cadence will also participate in several partner booths, including:

  • ChipEstimate.com - Booth 1202
  • TSMC - Booth 2430
  • ARM - Booths 1414 and 802
  • GLOBALFOUNDRIES - Booth 303
  • Samsung - Booth 2001
  • TowerJazz - Booth 1105
  • Si2 - Booth 1214

Attend Cadence breakfasts and luncheons to explore challenges and solutions in the critical areas of advanced node design, custom IC design, mixed-signal design and verification, and system development. Cadence, its customers, and ecosystem partners will share project experiences and successes at a series of events. To register, click here.

Monday, June 4 Luncheon - Overcoming Variability and Productivity Challenges in Your High-Performance, Advanced Node, Custom/Analog Design Speakers: Francois Lemery, CAD Project Manager, STMicroelectronics, Vinod Kariat, Fellow, Cadence, Thomas Volden, Architect, Cadence Time: 11:30 AM - 1:00 PM Location: 270-276 (Moscone Convention Center)

Tuesday, June 5 Breakfast - Addressing Hardware/Software Co-Development, System Integration, and Time to Market Speakers: LSI Corp and Cadence Time: 7:30 AM - 10:00 AM Location: 270-276 (Moscone Convention Center)

Tuesday, June 5 Luncheon - Overcoming the Challenges of Embedding Ultra Low-Power, ARM 32-bit Processors into Analog/Mixed-Signal Designs Speakers: Rob Cosaro, MCU System and Architecture group, NXP, Keith Clarke, VP Embedded Processors, ARM, John Murphy, Alliance Group Director, Cadence, Mladen Nizic, Engineering Director, Cadence, Jamie Davey, ARM Alliance Director, Cadence Time: 11:30 AM - 1:00 PM Location: 270-276 (Moscone Convention Center)

Wednesday June 6 Breakfast - The Path to Yielding at 2(x)nm and Beyond Speakers: Cadence, IBM, Samsung Time: 7:30 AM - 9:00 AM

Location: 270-276 (Moscone Convention Center)

 

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