CIMdata PLM Industry Summary Online Archive

10 July 2012

Implementation Investments

ATopTech Selects Berkeley Design Automation Analog FastSPICE™ Platform to Enhance Aprisa Place and Route for 28nm/20nm Processes

Berkeley Design Automation, Inc. today announced that ATopTech, has selected the company’s Analog FastSPICE (AFS) Platform to enhance the accuracy of the timing analysis in Aprisa place and route product for designs at advanced process technology nodes, such as 28nm and 20nm.

 “Aprisa’s timing-driven place and route technology is constantly calibrated for SPICE-level accuracy at advanced technology nodes,” said Jue-Hsien Chern, CEO at ATopTech. “We selected the Analog FastSPICE Platform for the calibration of Aprisa’s timing-driven place and route technology for 28nm/20nm because it delivers nanometer SPICE accuracy more than 5 times faster than traditional SPICE and has the capacity required for large post-layout calibration runs.”

The Analog FastSPICE Platform provides circuit verification for nanometer analog, RF, mixed-signal, and custom digital circuits. Foundry certified to 20nm, the AFS Platform delivers nanometer SPICE accuracy 5x-10x faster on a single core and >2x faster on multicore systems versus any other simulator. For circuit characterization, the AFS Platform includes the industry’s only comprehensive silicon-accurate device noise analysis and delivers near-linear performance scaling with the number of cores. For large circuits, it delivers >10M-element capacity, the fastest near-SPICE-accurate simulation, and the fastest, most accurate mixed-signal simulation. Available licenses include AFS circuit simulation, AFS Transient Noise Analysis, AFS RF Analysis, AFS Co-Simulation, and AFS Nano SPICE.

“We are excited that ATopTech selected the AFS Platform for characterization and calibration of their timing analysis engine,” said Ravi Subramanian, president and CEO of Berkeley Design Automation. “Accurate timing closure and sign-off is critical to IC designers and ATopTech’s selection highlights the accuracy, performance, and capacity benefits of the AFS Platform.”

About ATopTech

ATopTech was founded in 2004 by a team of leading EDA physical design implementation experts expressly to build new technology, from scratch, to deal with these issues design at 65nm and below. Aprisa, the result of these efforts, shipped to customers in December 2006 and has been used successfully in several hundred tapeouts to date. Aprisa is currently in active use in several 28nm design efforts. Apogee, launched in 2009, is a complete top down floorplanning and chip assembly tool that complements Aprisa. It has been used successfully in several dozen tapeouts. For more information, visit http://www.atoptech.com

 

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