CIMdata PLM Industry Summary Online Archive
17 July 2012
Implementation Investments
Fujitsu Semiconductor Selects Cadence Signoff Solution for Its Newest Reference Design Flow
Cadence Design Systems, Inc. announced today that Fujitsu Semiconductor Limited adopted the Cadence® Encounter® Timing System for timing signoff after engineers from Fujitsu Semiconductor and Fujitsu VLSI Limited, a group company of Fujitsu Semiconductor, completed a comprehensive competitive benchmark across a series of ASIC/ASSP and SoC designs. Using Cadence technology, Fujitsu Semiconductor said that 99% of hold violations were resolved after just one iteration through the ECO flow. In addition, negligible impact was made to setup time, and better routability was achieved when compared to another vendor's signoff product. Cadence Encounter Timing System delivered comprehensive physically-aware, multi-mode, multi-corner (MMMC) analysis across the design flow, engineering change orders (ECOs), and final signoff.
Timing signoff closure has become an increasingly significant bottleneck due to the increase in modes and corners required for analysis and the divergence of timing results between implementation and signoff timing tools. Furthermore, the complexity of today's designs requires the ability to do complete physically-aware MMMC signoff during ECO for rapid timing closure. To accomplish this requires a deep integration between physical and signoff design tools and a fundamentally new approach to software architecture. All of this can be done today uniquely with Cadence Encounter Timing System. The Encounter Timing System's physically aware timing ECO met Fujitsu's qualification criteria, and was incorporated into its production reference design flow.
"After a careful qualification study, we determined that Cadence signoff technology is a very effective path to get our chips to signoff closure," said Akihiro Yoshitake, vice president, SoC Design Engineering Division, IP & Technology Development Unit at Fujitsu Semiconductor Limited. "Multi-mode, multi-corner timing analysis and physically aware signoff timing optimization provide the key elements in fixing the remaining timing violations at the final timing verification stage. We expect the Cadence signoff solution, which includes these features, will drive further timing closure efficiency improvements in our design flow."
Cadence Encounter Timing System and QRC Extraction are important elements within the design implementation environment. The tight integration between them improves timing convergence throughout the design flow and greatly reduces time to design closure. While traditional flows require a serial, multi-step iterative process between physical implementation and signoff, the integrated signoff technology inside the Cadence digital implementation flow enabled Fujitsu Semiconductor to reduce the number of ECO loops due to deterministic placement of new cells while optimizing performance and area for its large, high-performance designs.
"At the latest advanced nodes, a comprehensive multi-mode, multi-corner optimized design and signoff ECO flow is a must-have to keep design schedules under control and to deliver superior results in silicon," said Dr. Chi-Ping Hsu, senior vice president, Silicon Realization Group at Cadence. "Encounter Timing System uniquely offers this capability today and delivers a significant competitive advantage for our users. We are pleased to be working closely with leading companies like Fujitsu Semiconductor to help drive these exceptional time-to-market and quality-of-silicon results."
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