CIMdata PLM Industry Summary Online Archive
17 January 2012
Company News
Cadence Publishes Definitive Book on Advanced Verification for Today's ICs
Cadence Design Systems, Inc. announced that it has published a new book to aid verification engineers. "Advanced Verification Topics" describes in great detail the latest techniques and methodologies for verifying today's most complex IP and systems on chips (SoCs). Penned by eight Cadence verification experts, "Advanced Verification Topics" builds on the prior Cadence® book, "A Practical Guide to Adopting the Universal Verification Methodology (UVM)." The new book delves into such topics as metric-driven verification of digital and mixed-signal designs, low-power verification using the UVM, multi-language UVM, and acceleration for the UVM.
"With the march toward greater design complexity showing no sign of abating, comprehensive verification is essential for a company to achieve its profitability goals," said Hao Fang, IP design manager at LSI. "'Advanced Verification Topics' will be an important reference book for teams responsible for verifying complex mixed-signal IP and SoCs that utilize low-power, verification IP (VIP), transaction-level models (TLM), acceleration, and similar techniques to reduce risk while getting end products into working silicon faster."
The 229-page "Advanced Verification Topics" is available now at Amazon.com and Lulu.com.
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