CIMdata PLM Industry Summary Online Archive
25 September 2012
Product News
ProPlus Design Solutions Unveils Innovative Design for Yield Software
ProPlus Design Solutions, Inc., provider of Design for Yield (DFY) solutions that integrate device modeling, parallel SPICE simulation and statistical analysis, today unveiled NanoYield™, fast and accurate yield prediction and optimization software for memory, logic, analog and digital circuit design.
Faster than traditional Monte Carlo analysis for both regular three-sigma and advanced six-sigma analysis, NanoYield is part of ProPlus Design Solutions' transistor-level statistical modeling and design and variations-aware product portfolio. It features High Sigma analysis, advanced Monte Carlo analysis and NanoSPICE™ parallel SPICE simulator to accelerate statistical simulation performance.
"The addition of NanoYield rounds out our product portfolio, solidifying our position as the only company to offer device modeling, SPICE simulation and DFY analysis integrated into one tool suite," says Dr. Zhihong Liu, executive chairman of ProPlus Design Solutions. "We are the only company to offer all three solutions."
Introducing NanoYield
NanoYield can be integrated into an existing design flow and predicts yield at early design stages, enabling engineers to evaluate and optimize integrated circuit (IC) designs for optimum yield and performance tradeoffs.
It includes innovative algorithms and parallel technologies to accelerate statistical simulation performance. NanoYield's engine is the NanoSpice parallel SPICE simulator and contains Monte Carlo Pro (MC-Pro) technology with parallel processing that can deliver 10 to 100 times acceleration over traditional Monte Carlo products. Its High Sigma Pro (HS-Pro) feature licensed and validated by IBM increases high-sigma (e.g., 5-6 sigma) statistical simulation performance by 103 to 106 times, offering accurate predictions of the extreme low-failure rate of cell blocks. With HS-Pro, engineers can predict the yield of repetitive structure circuits, such as memory where small cell failure rate is necessary but not predictable by practical Monte Carlo runs.
The NanoYield design flow starts with circuit design and simulation. Engineers input nominal design and statistical models that represent process variations into NanoYield to calculate process, voltage and temperature (PVT) variations and run Monte Carlo statistical simulations. A report will highlight yield estimations, output distributions and sensitivity and failure analysis, along with some guidelines for optimized designs. Engineers can iterate the design to further optimize it within the NanoYield flow until it meets yield and performance targets.
NanoYield takes input from the command line, the Cadence Virtuoso® Analog Design Environment or NanoExplorer, a design exploration and analysis environment used to validate and analyze models and circuit blocks. It is fully compatible with HSPICE from Synopsys and Cadence's Virtuoso Spectre® format inputs.
ProPlus Design Solutions has integrated advanced device modeling, a high-performance SPICE engine and hardware-qualified sampling algorithms into one DFY solution for faster and more accurate statistical analysis. In addition to its circuit simulation software, its product portfolio includes three SPICE modeling solutions. BSIMProPlus™ is the de-facto golden SPICE model extraction and validation platform. NoisePro™/9812B is the de-facto golden low-frequency noise characterization and modeling system. Model Explorer™ is a model validation and evaluation tool.
For more information, visit www.proplussolutions.com.
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