Cadence Design Systems, Inc. today announced that Renesas Electronics Corporation has adopted the Cadence® Interconnect Workbench (IWB) to accelerate performance analysis and verification of their on-chip interconnects by up to 50 percent. Interconnect Workbench provided Renesas with a cycle-accurate performance analysis of interconnect throughout the system on chip (SoC) and micro controller design process by quickly identifying bottlenecks under critical traffic conditions, enabling Renesas to improve device performance and reduce time to market.
"As design complexity increases with more and more IP integrated on a single chip, accurate performance analysis of off-chip memory access and on-chip interconnect becomes more crucial," said Toshinori Inoshita, senior manager, Elemental Technology Development Div. 1, Renesas System Design Co., Ltd. "Cadence Interconnect Workbench is a unique tool which allowed us to accurately monitor the performance of on-chip interconnect, dramatically improving turn around time for design architecture exploration. We're planning to adopt this technology on additional new design projects at Renesas."
Prior to adopting Cadence Interconnect Workbench, Renesas used a traditional methodology to develop performance verification environments and analyze the results. With their previous approach, they analyzed performance at IP, sub-system, chip design cycle independently. Interconnect Workbench, used in conjunction with the Cadence Incisive® Enterprise Simulatorand vManager™ planning and metrics, enabled early detection of performance issues and early validation of system performance requirements on an integrated environment. Renesas also used Interconnect Workbench together with the Cadence Palladium® Z1 Enterprise Emulation Platform to accelerate the application-level performance analysis and verification with emulating software loads on their design.
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