Synopsys, Inc. announced its analog design migration flow is enabled across TSMC's advanced process technologies, including N4P, N3E, and N2. The analog design migration flow, part of the Synopsys Custom Design Family, includes a machine learning-based schematic and template-based layout migration solution to speed up overall analog design migration tasks. As part of the design migration solution, the integrated parasitic-aware, AI-driven optimization technology helps overcome the manual and iterative effort typically required to tune analog designs to meet all specifications. Using the flow, engineers can optimize their design in the new technology node while shaving weeks off engineering time and effort.
"With the significant performance and power efficiency advantages of TSMC's most advanced process technologies, design teams can bring innovative chips to life that are in high demand for today's smart, connected, and compute-intensive applications," said Dan Kochpatcharin, head of the Design Infrastructure Management Division at TSMC. "Our long history of collaboration with Synopsys continues to benefit mutual customers who are migrating existing analog designs to next-generation TSMC processes, with productive and time to market gains."
"Increased chip complexities, engineering resource constraints, and tighter delivery windows are driving companies to AI-driven solutions to help accelerate quality of results and time to results," said Sanjay Bali, vice president of Strategy and Product Management for the EDA Group at Synopsys. "Our collaboration with TSMC on the analog design migration flow for TSMC's N4P, N3E, and N2 processes enables mutual customers to unlock massive productivity gains with efficient migration of their designs from node-to-node."
Enabling Efficient Migration of Analog and IP Designs
Last fall, Synopsys was recognized as a TSMC OIP Partner of the Year; among the achievements highlighted was the certified Synopsys Custom Design Family, which provides machine learning-based schematic and template-based layout migration capabilities for efficient reuse of existing IP when migrating analog designs across TSMC advanced nodes. Key components of the analog design migration flow include Synopsys Custom Compiler design and layout solution, Synopsys PrimeWave™ design environment, and Synopsys PrimeSim™ circuit simulation solution, which are enabled for all TSMC advanced FinFET technologies and deliver a performance advantage in SPICE, FastSPICE, and mixed-signal simulation.
Facilitating an Early Start on Designs
With the availability of interoperable process design kits (iPDKs) tuned to TSMC's N4P, N3E and N2 processes, analog design teams can start their projects earlier and be on a highly productive path. Mutual customers using the iPDKs can use the best-in-class tool in their flows, simplify the development flow, and cut turnaround time. In addition, an enabled RFIC reference flow for the TSMC N4P RF FinFET process, developed in partnership with Ansys and Keysight, is now available for TSMC customers to accelerate RF designs. The open RF design flow enables RF SoC design engineers to meet performance, power efficiency, and time-to-market requirements.
