Mentor Graphics Corporation (NASDAQ: MENT) today announced the immediate availability of the EZ-VIP productivity package for ASIC and FPGA verification teams using Questa® Verification IP (QVIP). This package increases productivity by reducing the time spent creating, instantiating, configuring and connecting up a QVIP testbench by 5X or more. This means verification teams have more time available to use QVIP to verify that their design is functionally correct.
The EZ-VIP package consists of QVIP Configurator software, a VIP bring up service package and a new EZ-VIP API. The QVIP Configurator software creates, instantiates and configures UVM testbenches for all protocols in the QVIP library, including PCIe, AMBA, USB, Ethernet, MIPI and Memory protocols, avoiding the time-consuming and error-prone process of writing these testbenches by hand. In many verification projects, a complicated end-to-end UVM verification infrastructure has to be created before a single test can be written. The bring up service package leverages the Mentor® protocol expertise and experience to allow project teams to start from a working, connected end to end testbench. This means verification teams can be productive writing tests immediately. The new EZ-VIP API provides easy-to-use stimulus, transaction logging, and delay control, so that test writers can focus on the behavior of their tests without being delayed by the complexity of UVM.
“We have been highly productive using Mentor’s QVIP library,” said Sundararajan Haran, engineering manager of logic verification and ASIC for Microsemi Corporation. “With other tools in Mentor’s Enterprise Verification Platform such as Questa Portable Stimulus Solutions combined with VIP, Verification Management and Formal Solutions, we have been able to rapidly verify different configurations for our SoC FPGA product families.”
The Questa VIP library provides engineers with standard UVM SystemVerilog (SV) components using a common architecture across all supported protocols. This allows rapid deployment of multiple protocols within a verification team. Test plans, compliance tests, test sequences and protocol coverage are all included as SV and XML source code, allowing simple re-use, extension and debug. The Mentor VIP components also include a comprehensive set of protocol checks, error injection and debug capabilities.
“Verification IP is key component of our Enterprise Verification Platform, which provides a complete verification solution from virtual prototyping to simulation, emulation, FPGA prototyping and post-silicon debug,” said John Lenyo, vice president and general manager, Design Verification Technology Division, Mentor Graphics. “The EZ-VIP productivity package means that our customers can achieve their verification goals quickly and reliably.”
