Synopsys, Inc. today announced that it has achieved certification and compliance from multiple standard organizations for a broad range of DesignWare® IP on the TSMC 16-nm FinFET Plus (16FF+) process including USB 2.0 and USB 3.0, PCI Express® 3.1, HDMI 2.0, MIPI® D-PHYSM and Serial ATA (SATA™) IP solutions. The IP have passed all the required tests for certification and compliance through independent authorized test centers sponsored by USB-IF, PCI-SIG Interoperability Workshops, HDMI Licensing, LLC and SATA-IO standards organizations. By achieving certification of its DesignWare IP, Synopsys gives designers confidence that the IP is interoperable and functions as expected in the TSMC 16FF+ process.
"Synopsys' availability of Certified DesignWare IP on TSMC's 16FF+ process further demonstrates its commitment to providing high-quality IP solutions that help designers speed development of SoCs on TSMC's advanced FinFET processes," said Suk Lee, TSMC senior director, design infrastructure marketing division. "With silicon-proven DesignWare IP for TSMC's 16FF+ process technology, designers can benefit from the performance, power and area advantages of our process while reducing integration risk and delivering differentiated products to the market faster."
"As a member of USB-IF for close to 20 years, Synopsys continues to actively drive and promote the adoption of the USB interface," said Jeff Ravencraft, USB-IF president and chief operating offficer (COO). "The certification of the Synopsys DesignWare IP for USB demonstrates that it meets all interoperability tests and functions as expected, enabling designers to integrate the USB interface into their SoCs with confidence."
"We are pleased that Synopsys' DesignWare IP for PCIe 3.1 technology has passed compliance testing," said Al Yanes, PCI-SIG chairman and president. "Companies such as Synopsys that participate in PCIe compliance testing help ensure interoperability, contribute to the continued expansion of the PCIe ecosystem and ultimately increase I/O performance for the next-generation of devices."
"Synopsys' DesignWare HDMI IP solution passed the stringent requirements of the HDMI 2.0 Compliance Test Specification at the GRL-Philips Authorized Test Center," said Quintin Anderson, co-founder and chief operating officer at Granite River Labs. "Passing compliance gives designers confidence that the HDMI IP in the TSMC 16FF+ process is robust and interoperable, while supporting the latest functionalities of the HDMI 2.0 standard."
"Synopsys has been an active member of the MIPI Alliance working groups for over 10 years, contributing to the development and driving the adoption of MIPI specifications," said Joel Huloux, chairman of the board of MIPI Alliance. "Synopsys helps designers integrate IP that is compliant to the D-PHY v1.2 specification into their SoCs for high-end mobile, consumer and automotive image sensor and display applications with less risk."
"The DesignWare SATA IP has successfully passed the SATA-IO's extensive interoperability test program," said John Calvin, chairman, SATA-IO Interoperability Working Group. "Designers can confidently work with this product knowing that it adheres to the SATA specification and meets interoperability requirements for successful SoC integration."
"With more than 45 FinFET tapeouts to date, Synopsys makes significant investments in delivering certified and compliant IP to help designers reduce their integration risk," said John Koeter, vice president of marketing for IP and prototyping at Synopsys. "The certification of DesignWare IP for USB, PCI Express technology, HDMI, MIPI and SATA on the TSMC 16FF+ process underscores our commitment to providing high quality, interoperable IP that enable designers to meet their schedule goals and achieve first-pass silicon success."
