Cadence Design Systems, Inc.today announced it plans to showcase its ARM®-optimized solutions that make complete systems possible at ARM TechCon 2015. The event is scheduled for November 10-12, 2015, in Santa Clara, Calif., with Cadence, a diamond sponsor, in booth #200.
WHAT:
Cadence is scheduled to deliver several presentations developed for the ARM community. The scheduled Cadence® speaking sessions are:
- Case Study: Optimizing GPU Performance Through Matched DDR Subsystem Design: Tuesday, Nov. 10, 11:30am, Nick Heaton, Cadence distinguished engineer, and Mladen Wilder, ARM senior principal engineer
- Miniaturizing Sensing and Power for IoT Design: Wednesday, Nov. 11, 10:30am, Ian Dennison, Cadence senior group director, R&D, and Tim Menasveta, ARM CPU product manager
- Multi-Abstraction Hardware/Software Debug for ARMv7/8-Based SoCs: Wednesday, Nov. 11, 11:30am, Frank Schirrmeister, Cadence group director, product management, Larry Melling, Cadence product management director, and Robert Kaye, ARM technical specialist
- High-Performance Implementation of ARM Cortex®-M7 Processor in Embedded Flash Technology, Wednesday, Nov. 11,11:30am, Emmanuelle Amouriaux, Cadence staff applications engineer, and Alain Sermesse, Atmel physical design manager
- Reducing Margin Pessimism in ARM IP with LVF and Statistical On-Chip Variation: Wednesday, Nov. 11, 2:30pm, Igor Keller, Cadence distinguished engineer, and Jim Dodrill, ARM senior principal engineer
- Validating the Performance Envelope of Configurable Cache-Coherent Systems: Wednesday, Nov. 11, 3:30pm, Nick Heaton, Cadence distinguished engineer and Jeff Defilippi, ARM product manager
- New Verification Requirements for ARM AMBA® AHB-Based IoT Systems on Chip (SoCs): Wednesday, Nov. 11, 4:30pm,Avi Behar, Cadence product marketing director, Verification IP, and William Orme, ARM product manager
- Achieving Perfect Power/Performance/Area/Thermal Balance for Apps Processor Cores in FinFET Nodes: Thursday, Nov. 12, 10:30am, Sumit Goswami, Qualcomm engineering director
- Practical ARM CPU Digital Implementation on TSMC 10nm: Thursday, Nov. 12, 11:30am, Paddy Mamtora, Cadence product engineering group director, and Tim Whitfield, ARM director of engineering
- Portable and Reusable System-Level Verification Use Cases for ARM-Based SoCs: Thursday, Nov. 12, 11:30am, Larry Melling, Cadence product management director, and, Swami Venkatesan, solutions architect
- Implementation of ARM Cortex-A17 Quad-core in GLOBALFOUNDRIES 22FDX Technology: Thursday, Nov. 12, 2:30pm, Dr.Joerg Winkler, GLOBALFOUNDRIES fellow design engineer, and Dr. Tamer Ragheb, GLOBALFOUNDRIES digital design methodology manager
- Architecting and Customizing SoC Infrastructure for Optimum Mobile SoC Performance: Thursday, Nov. 12, 2:30pm, Nick Heaton, Cadence distinguished engineer, and William Orme, ARM strategic marketing manager, Interconnect Products
- Enabling Power Closure and Power Analysis for ARM Systems: Thursday, Nov. 12, 4:30pm, John Decker, Cadence low-power solutions architect
New this year is the Cadence "Expert Bar" in booth #200, where attendees can hold in-depth discussions on a variety of design challenge topics with Cadence experts. Throughout the two exhibit days, experts will be available on topics such as IoT design, verifying AMBA protocol compliance, embedded software debug and digital implementation of ARM IP. To see the full schedule, visit the Cadence events website at http://www.cadence.com/cadence/events/Pages/event.aspx?eventid=1008.
To register for the conference, visit http://www.armtechcon.com
WHEN:
ARM TechCon is scheduled for November 10-12, 2015.
WHERE:
Santa Clara Convention Center in Santa Clara, Calif.
Cadence is located in booth #200.
