Synopsys, Inc. today announced that Synopsys' custom design platform has been certified by Samsung Electronics for its 28FDS (FD-SOI) process technology. The certified Synopsys custom design platform includes HSPICE® golden-accuracy circuit simulation, Custom Compiler™ visually-assisted layout automation, StarRC™ gold-standard parasitic extraction and IC Validator scalable physical signoff. The Synopsys custom design platform provides improved custom and mixed-signal design productivity for Samsung 28FDS users designing for various low power required applications such as IoT and Connectivity.
Custom Compiler's user-guided symbolic editing technology accelerates 28FDS device placement. It includes interactive custom routing technology that can quickly create DRC-correct routing, thus reducing late-stage physical signoff iterations. The combination of placement and routing assistants in the Custom Compiler solution cuts 28FDS layout effort by up to 30 percent. Custom Compiler support for these advanced features is provided through a jointly developed 28FDS process design kit (PDK) in the industry-standard interoperable process design kit (iPDK) format.
"Samsung Foundry's 28FDS delivers lower design cost, lower total power and better analog performance, making it suitable especially for low power driven applications such as IoT and connectivity," said Jaehong Park, senior vice president of the Foundry Design Team at Samsung Electronics. "We worked with Synopsys to certify Synopsys' custom design platform for our 28FDS process technology to enable our customers to accelerate their custom design development."
Synopsys' custom design platform offers advanced features to improve reliability and manage variability for automotive and IoT designs. Comprehensive aging simulation and Monte Carlo analysis is driven by a common simulation environment, making it easier to analyze reliability. Advanced reporting, cross-probing and visualization features enable automotive designers to identify and solve reliability problems faster. Accurate net-based parasitic extraction with the StarRC tool during layout helps control design variability with little iteration. The Custom Compiler In-Design assistant with IC Validator catches DRC violations during layout and reduces physical signoff iterations. The platform also enables the use of simulation results to directly check electromigration effects during layout.
"Samsung Foundry's certification of Synopsys' custom design platform is important to our mutual customers developing complex designs," said Bijan Kiani, vice president of product marketing at Synopsys. "Through close collaboration, we have delivered a certified custom tool suite and accompanying iPDK to enable our mutual customers to improve their custom layout and circuit simulation productivity."