CIMdata PLM Industry Summary Online Archive

2 December 2009

Product News

Magma Announces Talus-Based RTL-to-GDSII Reference Flow for Imagination Technologies' POWERVR Graphics Accelerator -- Delivers Repeatable Results, Speeds Deployment

Magma(R) Design Automation Inc. announced the availability of an RTL-to-GDSII reference flow for system-on-chip (SoC) designs that incorporate POWERVR™ SGX graphics accelerator cores from Imagination Technologies, a leader in SoC intellectual property (IP). Based on Talus(R) 1.1, the latest release of Magma's design implementation system, the flow leverages the recently enhanced optimization capabilities of the Talus Design 1.1 synthesis tool and the Talus COre™ technology that performs timing optimization concurrently during routing.

Also included is the Talus Flow Manager™ which provides an out-of-the-box reference flow that engineers can quickly and easily tune for their specific SGX-based designs. With the reference flow and Imagination Technologies' POWERVR graphics processors, designers can achieve faster overall design closure with better performance and predictability for their consumer and wireless multimedia processing applications.

"The drive to get to market faster than the competition is stronger than ever, so our customers don't have time to waste setting up and validating design flows," said Martin Ashton, vice president of POWERVR Visual IP at Imagination Technologies. "With the Talus-based reference flow, our customers can design and deliver innovative SoC devices utilizing the industry's most advanced graphics acceleration technologies in record time."

"Dealing with the complexities of 65-nanometer and smaller process geometries is a significant challenge," said Premal Buch, general manager of Magma's Design Implementation Business Unit. "By incorporating advanced capabilities such as early clock tree modeling, advanced crosstalk optimization, concurrent optimization during routing into Talus 1.1, and providing reference flows, Magma is equipping designers with the technology they need for silicon success."

The reference flow is available now from Magma. Please send e-mail to sales@magma-da.com for more information.

Talus: Fastest Path to Silicon™

Talus 1.1 was created to deliver optimal quality of results out of the box at advanced process nodes. It has already been used to tape out numerous production chips at 40 nanometers (nm), and is ready for designs at 32 nm and 28 nm.

Talus Design and Talus Vortex are key components of Magma's RTL-to-GDSII system. Talus Design performs RTL synthesis and physical optimization. Talus Vortex performs placement, clock tree synthesis and routing.

Talus COre Technology

The heart of the improvements in Talus 1.1 is its Concurrent Optimizing Routing Engine (COre) technology. At advanced geometries, complex resistance effects, increased via resistance and crosstalk can create a large timing disconnect between placed gates and final routing. Dealing with optimization and routing sequentially results in a suboptimal solution with unpredictable results. Traditional solutions optimize the design after routing to get the necessary accuracy, lengthening runtimes. Leveraging Magma's unique unified data model architecture, Talus COre applies the full scope of timing optimization concurrently during routing. Every aspect of the routing algorithms -- from topology generation to layer assignment, track assignment and DRC cleanup -- is timing and crosstalk aware. This allows design convergence and eliminates post-route timing surprises. Talus COre is coupled with Talus' Standard Delay Format (SDF)-based optimization to remove the need for manual engineering change orders (ECOs) to close timing.

The addition of the Talus COre technology allows Talus 1.1 to deliver optimal quality of results out of the box for designs implemented in advanced process technologies. It has already been used to complete production designs where it provided runtime that was more than 5 times faster than competitive solutions. In customer beta testing on 40-nm designs ranging from 2 million to 4 million gates, with frequencies from 400 MHz to 800 MHz, Talus 1.1 produced 75 percent better timing with 10 percent fewer vias than competitive tools.

Talus Flow Manager

Talus 1.1 also introduces the new Talus Flow Manager that provides an out-of-the-box Talus RTL-to-GDSII design flow tuned to deliver optimal results. Designers can easily customize the reference flow and tailor it to their own requirements, developing specific flows for various projects or applications. Additional reference flows include templates for the implementation of multiple-voltage (MVdd), multiple-mode and multiple-corner (MMMC) designs, as well as low-power and high-performance designs. Ease of use and cost of adoption is dramatically improved through the use of these pre-qualified flows.

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